[PCB_FORUM] Re: electrical constraint manager, timing

From: SjChar3@xxxxxxxxxxxx
To: icu-pcb-forum@xxxxxxxxxxxxx
Date: Tue, 05 Jul 2005 14:14:59 -0400
Here are some of the numbers i'm getting.

Net Name:       PIPE_0_RXD6

  Via Count:              6
  Total Etch Length:      3538.836 MIL
  Total Manhattan Length: 3103.598 MIL
  Percent Manhattan:      114.02%

 Net Name:       PIPE_0_PCLK

  Via Count:              6
  Total Etch Length:      3999.72 MIL
  Total Manhattan Length: 2576.304 MIL
  Percent Manhattan:      155.25%




"Austin Franklin" <austin@xxxxxxxxxxxx> wrote:

>Under net/routing/relative prop delay, set up a group that contains your
>clock and other signals you want related to this clock.  Set the group match
>length value in the group name heading under "delta:tolerance", such as
>"0:-300" (note the "=", typically 300 will mean +- 300), and it will then be
>assigned to all the signals in that group.  Then, select the clock and set
>it as "target".
>
>Regards,
>
>Austin
>
>> -----Original Message-----
>> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
>> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of
>> sjcharles@xxxxxxx
>> Sent: Thursday, June 30, 2005 11:12 AM
>> To: icu-pcb-forum@xxxxxxxxxxxxx
>> Subject: [PCB_FORUM] electrical constraint manager, timing
>>
>>
>> Group: how do i set up a constraint for my clock signal to arrive
>> at it destination where it is equal to or less the arrival of the
>> data signals.
>> I'm using pcb si 610. any suggestions would be appreciated.
>> Thanks, Sam
>
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[PCB_FORUM] Re: electrical constraint manager, timing

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