[PCB_FORUM] Re: Using an "Electrical CSET" vs a "Constraint Set" for diff pairs...

  • From: "richard moffat" <richard.moffat@xxxxxxxxxxxxxxxxxxx>
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Thu, 27 Mar 2008 10:22:29 +1200

Hi

Constraints for Diff pairs are more straightforward in v16, once you get used to it.  The major advantage is that all constraints are now grouped together in the one spreadsheet.

The idea is to define a Physical Constraint Set (PCSet), similar to an ECSet, and assign that to the diff pairs.

I can't immediately find an example of different trace widths/spaces (we have done them), but here's a screenshot to give you an idea.  We migrated to 16.0 almost purely for the reason of a more integrated Constraint Manager.

Hope this helps.
 
Cheers,
Richard






 
 
__________________________
Richard Moffat
PCB CAD Team Leader
Allied Telesis Labs
ph. +64 (3) 3393000
richard.moffat@xxxxxxxxxxxxxxxxxxx

>>> On 27/03/2008 at 7:17 a.m., in message <D52F1F6C17B8D24EB3ECC387E1DE4E458D7D72@xxxxxxxxxxxxxxxxx>, "Macindoe, Gary" <Gary.Macindoe@xxxxxxx> wrote:

Hey Austin,

You know, Ive wondered about that. Luckily I havent had to deal with it yet.
One reason is that lately I only have top and bottom as routing layers.
I think the last time I had inner layers, the stack-up was designed to have the trace widths/spaces the same for inner and outer for all impedances.

Heres how I handle it now for only outer routing layers, on 15.5.1:

-          I set up the diff pairs using Logic -> Assign Differential Pair, Auto Generate

-          I set the trace width, spacing etc. for the pairs in CM

-          I create a Spacing Constraint Set for each impedance (i.e. 90DIFF for USB) with the Line To Line set to the spacing required pair to pair

Im not sure how to handle a different trace width and spacing within the pair for inner layers as opposed to outer layers.

I would suggest, if you can, to design the stack-up to have the widths and spacings the same for outer and inner.
Thats the easy way out!

Maybe setting up constraints, including diff pairs, is easier in 16, I hope so.

Good luck, Im curious to see if anyone has the solution to this.


Gary E. MacIndoe
PCB Design Engineer
Fort Collins, Colorado
amd.com
gary.macindoe@xxxxxxx-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: Wednesday, March 26, 2008 12:39 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Using an "Electrical CSET" vs a "Constraint Set" for diff pairs...

Hi,

There appear to be two ways to get the diff pair spacing and gap, but only
one allows differing them by layer.  Setting up an "Electrical CSET" only
seems to allow one overall (as in for all layers) space/gap.  But, the
advantage of using the ECSET is you can assign it to a net or multiple nets
using the Constraints Manager spreadsheet using a pulldown menu.

Or, I can setup a "Constraint Set" and select each layer's space/gap...but I
then have to attach this as a property to each and every net manually by
selecting the nets and attaching this Constraint Set name as a
NET_PHYSICAL_TYPE attribute.

I prefer the Constraint Set, since it gives me the per layer control...but
the thing that seems to be missing, is the ability to assign a given
Constraint Set to the nets using the Constraint Manager spreadsheet.

I'm on 15.2.  Am I missing something?  If not, has this improved on 15.7 or
16?

Regards,

Austin

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