[PCB_FORUM] Re: Total number of pages in a hierarchical design
- From: "Khurana, Varun" <vkhurana@xxxxxxxxxxxx>
- To: "icu-pcb-forum@xxxxxxxxxxxxx" <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 20 Sep 2010 12:51:56 -0700
Chris,
Thank you - I was able to use cnEvalCustomVariables() to return a list of all
custom variables in the design, including TOTAL_DESIGN_SHEETS
I just need to know the value so this will work well - thanks again.
Varun
[cid:image001.png@01CB58C2.9B20F840]
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Shaw, Christopher
Sent: Monday, September 20, 2010 12:31 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Total number of pages in a hierarchical design
Hi Varun,
It depends what you want to do with the determined total page count value.
There is a built in variable called TOTAL_DESIGN_SHEETS which you can say add
to a page format symbol (using Text->Custom text) to show "sheet x of y"
information, where x would be the variable CURRENT_DESIGN_SHEET. I am not sure
if you can access these variables for anything else though.
Chris
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Khurana, Varun
Sent: Monday, September 20, 2010 2:10 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Total number of pages in a hierarchical design
Folks,
Is there a way to programmatically determine the total number of pages in a
hierarchical design in Allegro Design Entry HDL v16.3?
Counting page files in sch_1 folder is not an option since it won't work, if
the hierarchical symbol is instantiated more than once. Ideas are appreciated.
Thanks,
Varun
Qualcomm Inc.
San Diego, CA
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