[PCB_FORUM] Re: Removing unused pad rings on inner layers DURING design...
- From: "J Wages" <jwages@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 31 Mar 2005 15:55:37 -0500
Do you really need a 24 mil via? I've routed several 1mm on a standard
63 mil thick board and use 19 mil via pads with a 6 mil finished drill.
Jim S. Wages / SR. PCB Layout Designer:
Cary, NC - (919) 466-1596
-----Original Message-----
From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
Sent: Thursday, March 31, 2005 3:39 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Removing unused pad rings on inner layers
DURING design...
Hi Gerry,
> Oleg,
I think you mean Austin, as that is my response TO Oleg...
> Not sure what your motivation here is.
My motivation is to find if there is a solution available in the tool,
as
opposed to having to perform a "work-around" so I can route a board
using
standard design constraints using a tool that should allow me to do what
I
am trying to do. Apparently, the answer is no, the only solutions are
work-arounds.
It's simple arithmetic. 1mm BGA, 24 mil via pad, 10 mil drill, 4/4.5/4
mil
differential signals for 100 ohm impedance on inner layers for a 12
layer
board .062" thick. With the pad ring on inner layers, that leaves 39.37
-
12.5 - 24 = 2.87/2 for trace to pad clearance. That does not work.
Also,
not routing differential pairs together you lose the differential
coupling
for the distance it takes to get out of a BGA...which in some instances
can
be significant. With the unused pad rings removed during the design
process, this problem is alleviated.
> By properly defining your vias,
> line widths and spacings you should be able to route two lines through
> even 1mm BGAs (unless you boards have high aspect ratios).
I'm not sure what you mean by "properly". What I have defined for
design
parameters is perfectly "proper". So there is no confusion, I am
specifically speaking of routing between the dispersion VIAS (not the
BGA
pads) in a 1mm BGA field on the inner layers.
The trace width/spacing for differential pairs is determined by the
fabricator, with, of course, my input. I can not go below 4 mil trace
width, and this gives me a 4.5 mil differential gap, so that is what is
"proper" for the technology board I need to use. What is proper for the
via, again, for the technology I have to use, is 24 mil pad, 10 mil
drill.
So, again, simple arithmetic will not allow 4/4.5/4 AND proper pad to
trace
clearance between a 1mm BGA dispersion field with a 24 mil via ring. A
ring/drill/trace any smaller and that is outside the design
requirements.
Besides, as I've stated, it IS doable, and I have done it with no
problem,
but it requires additional work on my part to create and use the custom
padstacks.
> Attempting to
> use the drill hole as you clearance can be dangerous for high speed
> nets. You could actually get the line close enough to the hole that it
> is not referencing the plane. With dielectric thickness going down I
> find my line widths are actually getting too narrow.
If you mean impedance controlled, this is not an issue. The lines are
still
directly above/below the coupling plane. It's simply the trace to pad
clearance that causes a DRC violation...
> In really tight areas where you have trouble getting one line through
(<
> 1mm BGA etc.) I use a constraint area to define a smaller line to via
> spacing but also increase the line to line spacing in the constraint
> area to
> Not Allow a route past pins with connections on that layer. This will
> allow a route past unconnected pins and when the vias are removed you
> have your additional spacing.
That would "work", but as I've suggested, simply not having the pad
there
when it isn't used, is a very easy solution to this, and something that,
IMO, the tool should just do. If it can do it post layout, why not
during
layout?
Your suggested methodology, and my solution to use custom padstacks both
are
"work-arounds" IMO. The tool should just be able to do this, and not
require any work-arounds.
Regards,
Austin
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