Gary, You will need to add a PIN_DELAY property on the pins of the package that you have the delays for. This can be done as Peter described below for ConceptHDL and it can also be driven thru a 3rd party netlist or added manually to the pins using Edit > Properties. The field in CM will remain grayed out until pin pairs are generated after adding either a Rel Prop or Prop Delay rules or by creating a Pin Pair. Here is an example of a 3rd party netlist that can be read in incrementally using File > Import > Logic (Other Tab) $PINS $A_PROPERTIES PIN_DELAY 376.298 MIL ; U36.AF8 PIN_DELAY 452.969 MIL ; U36.AF6 PIN_DELAY 596.916 MIL ; U36.AK4 Remember to enable Pin Delay checks by opening the Electrical Constraint Set form accessed inside of Spacing/Physical Constraints. The setting will be under the Options tab. (Enable "Include in all Propagation Delays and DiffPair Phase Checks"). Sincerely, Michael Catrambone UTStarcom, Inc. Chairman Cadence Designer Network CDNLive! Worldwide Web Site: http://www.cdnlive.com <http://www.cdnlive.com> Cadence User Community Web Site: http://www.cdnusers.org <http://www.cdnusers.org> ________________________________ From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Peter Hughes Sent: Wednesday, April 18, 2007 9:51 AM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: Relative prop delay Hi Gary, In order to include the package lengths in a component you need to add them to the packages section of the schematic symbol. These values will then appear in the Pin Delay columns. Rgrds Peter Hughes, PCB Designer, Concurrent Technologies, 4 Gilberd Close, Newcomen Way, Colchester, Essex, CO4 4WN. Tel: +44 1206 752626 Fax: +44 1206 751116 -----Original Message----- From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Macindoe, Gary Sent: 18 April 2007 15:44 To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Relative prop delay Hey guys, It has reached the point where I have to consider the package length when matching some nets. I am using Relative Propagation Delay in CM, and was wondering if anyone knows how to include the package lengths? I thought maybe the Pin Delay columns, but they are grayed out. Any ideas? Regards, Gary Gary E. MacIndoe PCB Design Engineer Fort Collins, Colorado amd.com gary.macindoe@xxxxxxx