From my limited understanding, your assumption is correct and the key is achieving the correct (capacitive) coupling between the planes. Jim Wages wrote:
Ok, folks. Let me know if my thinking is wrong here.I have a 14 layer stack up. External etch layers are adjacent to power planes, which are adjacent to ground planes. Lyr 2 is a split power plane. Lyr13 is a solid 3.3V plane.Do you see any signal "return path" or integrity issues with routing a critical signal trace on the bottom layer as long as the driver of the signal was powered by 3.3V. What about a differential pair?I'm assuming that the power and gnd planes would be perceived as a short to hi-frequency signals, so that the return path would not have to get to a ground plane, but would just stay on the 3.3V plane directly beneath the trace until it returned to the driver.Thoughts? *//**/Jim S. Wages/* *SR. PCB Layout Designer*
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