[PCB_FORUM] Packaging with design constraints

  • From: "Coombs, William B. (US SSA)" <william.coombs@xxxxxxxxxxxxxx>
  • To: <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Thu, 3 Mar 2005 14:39:17 -0500

Hello all,

 

I'm a rookie Cadence user having a problem with packaging.

 

My design packaged fine until design rules were entered into the Constraint 
Manager.

Now when I try to package, the following error message appears; "failed to push 
electrical

constraints. Export Physical can't proceed."

 

Does anyone know the cause of this?

 

Thanks!

 

William B. Coombs

Sr. PCB Designer

BAE Systems CNIR

(973)636-7463

 

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