[PCB_FORUM] Re: Multi-GB topology

  • From: "Schwartz, Jerome" <jschwa01@xxxxxxxxxx>
  • To: "'icu-pcb-forum@xxxxxxxxxxxxx'" <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Wed, 20 Apr 2005 14:34:25 -0400

Andrew,
 
    I place anti-etch under these areas and use them with split planes.
 
 Regards,
      Jerry Schwartz, CID+
      IPC Advanced Certified Designer
     "May The Schwartz Be With You."

Designer 3
Harris Corporation GCSD              Voice (321)-727-5474
P.O. Box 37, MS 1/3232               Pager (321)-690-9797
Melbourne, FL 32902-0037           
mailto:Jerome.Schwartz@xxxxxxxxxx <mailto:Jerome.Schwartz@xxxxxxxxxx>

http://www.harris.com <http://www.harris.com/> 


-----Original Message-----
From: Andrew Noonan [mailto:andrew@xxxxxxxxxxx] 
Sent: Wednesday, April 20, 2005 2:00 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Multi-GB topology


With ever-increasing bit rates on high speed links, how are other designers
dealing with some of the more complex editing of planes for parasitic
capacitance reduction? Many connector manufacturers are suggesting things like
'dog-bone' shaped voids or rectangular voids encompassing both true and
compliment of a differential pair. 
 
Is this something that's on the roadmap for future versions of Allegro? 
Do some of you make the edits in Allegro?
Do some of you use post-processing tools to make the edits?
 
Thanks for you help,
 

Andrew Noonan
Sr. PCB Designer
Topspin Communications
(w)650-316-3398
(c)650-814-3677

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