[PCB_FORUM] Multi-GB topology
- From: "Andrew Noonan" <andrew@xxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 20 Apr 2005 11:00:27 -0700
With ever-increasing bit rates on high speed links, how are other
designers dealing with some of the more complex editing of planes for
parasitic capacitance reduction? Many connector manufacturers are
suggesting things like 'dog-bone' shaped voids or rectangular voids
encompassing both true and compliment of a differential pair.
Is this something that's on the roadmap for future versions of Allegro?
Do some of you make the edits in Allegro?
Do some of you use post-processing tools to make the edits?
Thanks for you help,
Andrew Noonan
Sr. PCB Designer
Topspin Communications
(w)650-316-3398
(c)650-814-3677
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