[PCB_FORUM] Re: Missing antipad definition
- From: "Cosentino, Tony" <Tony.Cosentino@xxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 16 May 2007 09:16:29 -0500
William,
If you decide to work in negative planes (as many companies do) you
should have a verified padstack library. Even if you have to sit down
and go through every padstack to qualify it meets the requirements for
your design type. Additionally, you should have a final artwork checking
procedure to verify that your final data passes a netlist check. I
prefer to use the IPC-D-356 output to do this verification. We use our
own tools to run this check and we also require our fabrication house to
run this check prior to creating masks for fabrication.
Thanks
Tony Cosentino
Tekelec
919-460-3656
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dave Seymour
Sent: Wednesday, May 16, 2007 10:06 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Missing antipad definition
One suggestion would be to include the IPC-356 netlist file with
your designs to the fab shop. Most board shops these days can
read and use the file.
The note on the fab drawing should state that the job goes on hold if
the netlist and the gerbers don't match. Saves much grief.
I know you got burned on these jobs, but the NULL is a valid
condition for certain designs.
Hope this helps.
Dave
William Billereau wrote:
Hello.
We use to work in negative mode with split panes and GND planes.
It's the case for more then 90% about our boards.
This week, 2 different jobs made by 2 different designers (made
on some weeks of gap, boards not designers! :-)) have feedback about the
same problem:
One the antipad of a power pad with slot drill is defined as
NULL, the other one the whole Layer 12 for a via_916 (from layer 9 to 16
in a 16layers board) is defined as NULL. (regular pad, thermal and
antipad)
So all vias in this layer are connected to copper planes! and
then all planes tied together. :-(((
We guess that in the second case the L12 has been added after
the editing of via_916.
Layers were defined as NULL everywhere in the 8th first layers
(1-8) but ALSO the "Default Internal layer"
Thus, when we inserted the 12th layer.... strange that none seen
it but it happened!
We use to remove thermal relief definition to make direct
connection for vias in negative planes.
This returns a WARNING! we accept and work with it.
It's a WARNING because it can be used like that...
But if you set an ANTIPAD to NULL it's also a simple WARNING!
It should be an ERROR for Cadence/Allegro!! and it must
dissallow the artwork!
Is there something we forgot to avoid this kind of things?
The one I see is to extract pads definition reports and look all
the lines to see if something is wrong (impossible to do "manually")
We can add a end check control and then view all pads definition
inside Allegro... but we have to add another check to check we did not
forget to check the first one ;-)
Is the only solution to work in positive mode?
Thanks.
William.
PS Subsidiary question: is there a way to check not redunded
vias but almost.
2 vias of the same net are close to same location (1.3mils
offset in an axis) but no DRC. Same net DRCs will produce close to 800
DRCs in this job.
William Billereau
CERN/TS-DEM
PCB Designer
--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560
Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297
Dave.seymour@xxxxxxxxxxxx
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