[PCB_FORUM] Re: Embedded Constraints within a Schematic for use within V15.1
- From: Michael.Catrambone@xxxxxxxxxx
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 9 Sep 2004 17:41:11 -0500
Good point but you do not have much control on where
these property get attached so if you have nets that span
multiple sheets it could be on any of them.
One final comment is that the interface is not truly bi-directional,
any deleted properties on either side cannot be forward or back
annotated so manual deletion is required.
"Leonard E Toohey (ltoohey)" <ltoohey
09/09/2004 03:04 PM
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Subject: [PCB_FORUM] Re: Embedded Constraints within a Schematic for use
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All of the properties can also be backannotated as well.
Once again you have to modify the .cfg file to get this to work for your
use.
-----Original Message-----
From: Michael.Catrambone@xxxxxxxxxx [mailto:Michael.Catrambone@xxxxxxxxxx]
Sent: Thursday, September 09, 2004 2:57 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Embedded Constraints within a Schematic for use
within V15.1
Importance: High
Shannon,
It can be done successfully.. We have been doing it for many many years as
far back as the Workview Office days.
You will need to find the Allegro.cfg file and verify that the following
lines are in the BeginAttPassList section. The default file that EPD uses
may contain some of these already and you may have to add some that are
missing.
The word NET followed by an Allegro Net property name is all you will
need..
Here is an example below:
NET BUS_NAME
NET ELECTRICAL_CONSTRAINT_SET
NET DIFFERENTIAL_PAIR
NET ECL
NET IMPEDANCE_RULE
NET PROPAGATION_DELAY
NET RELATIVE_PROPAGATION_DELAY
NET MIN_LINE_WIDTH
NET MIN_NECK_WIDTH
NET ROUTE_PRIORITY
NET TOTAL_ETCH_LENGTH
NET NET_PHYSICAL_TYPE
NET NET_SPACING_TYPE
NET MAX_PARALLEL
NET VOLTAGE
NET MAX_VIA_COUNT
NET NC
NET NO_TEST
We have not moved to EPD 3.1 yet but the process was the same when I was
testing EPD 3.0 One of the issues with EPD 3.X is Mentor started to
introduce some of the Mentor property names in the attribute editor so it
may be confusing at first but simply adding a properties to a wire inside
EPD will pass thru to the 3rd party netlist during compile. Beware of using
Pin to Pin delays with Relative Prop Delay and Prop Delay because it tends
to blow-up during absolute netlist import. If you are going to use
propagation delays on buses I would strongly suggest doing it via
Constraint
Manager in Allegro using Electrical Constraint Sets.
Hope this helps,
Michael Catrambone
UTStarcom, Inc.
"Abel, Shannon K." <shannon.abel
09/09/2004 02:17 PM
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Subject: [PCB_FORUM] Embedded Constraints within a Schematic for use
within V15.1
We are currently using EPD 3.1 (formerly viewlogic) as a schematic capture
program. We are trying to find out how to use the ability to transfer
embedded design constraints within the schematic to transfer over to
Allegro
v15.1.
Has anybody had any success with this or even tried it? I believe we need
a
config file in order to map those constraints (all 128 of them) into
allegro.
Shannon Abel
PWB Designer / Detailer
Northrop Grumman Electronic Systems
Marine Systems / PCS Division
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