[PCB_FORUM] Embedded Constraints within a Schematic for use within V15.1
- From: "Abel, Shannon K." <shannon.abel@xxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 9 Sep 2004 12:17:42 -0700
We are currently using EPD 3.1 (formerly viewlogic) as a schematic capture
program. We are trying to find out how to use the ability to transfer embedded
design constraints within the schematic to transfer over to Allegro v15.1.
Has anybody had any success with this or even tried it? I believe we need a
config file in order to map those constraints (all 128 of them) into allegro.
Shannon Abel
PWB Designer / Detailer
Northrop Grumman Electronic Systems
Marine Systems / PCS Division
-----------------------------------------------------------
To subscribe/unsubscribe:
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
with a subject of subscribe or unsubscribe
To view the archives of this list please login at
//www.freelists.org. Our list name is icu-pcb-forum
or go to //www.freelists.org/archives/icu-pcb-forum/
Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
Want to post a job listing ? DON'T DO IT HERE!
Better yet, join our jobs listing forum.
SUBSCRIBE: icu-jobs-forum-subscribe@xxxxxxxxxx
POST: icu-jobs-forum@xxxxxxxxxx
-----------------------------------------------------------
Other related posts:
