[PCB_FORUM] ET Marking

From: "Carrow, Dennis" <dcarrow@xxxxxxxxxx>
To: "'icu-pcb-forum@xxxxxxxxxxxxx'" <icu-pcb-forum@xxxxxxxxxxxxx>
Date: Wed, 22 Sep 2010 09:12:41 -0500

I'm guilty of calling out IPC-ET-652 on our fab drawing without having a copy 
to reference.  Does this document state that the tested board must be marked 
after testing?  Sorry if this is off our normal Cadence topics!  Thanks! -DC

Follow-Ups:
- [PCB_FORUM] Re: ET Marking
  - From: Schwartz, Jerome

Other related posts:

» [PCB_FORUM] ET Marking - Carrow, Dennis
» [PCB_FORUM] Re: ET Marking- Schwartz, Jerome