[PCB_FORUM] Re: Displaying non plated holes
- From: Dave Elder <dave.elder@xxxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Mon, 06 Sep 2004 15:32:20 +1200
Hi Steve,
We put a circle on the outline layer.
Cheers, Dave
steve kingdon wrote:
Hi,
Does anyone know how to display padless non plated holes in
Allegro? eg the hole for a plastic polarising pin.
We have done a bit of a work around by putting a resist layer
in the NP padstack slightly larger than the pin. Then you can turn
the resist layer on to see the (whole?) hole. Kind of painful.
From memory, in Veribest, hole visibility was controlled just like
any design element, on/off, colour etc.
Is there a way to do this in Cadence, or does anyone have
a better idea/solution?
Cheers,
Steve.
Steve Kingdon
PCB Designer
Allied Telesyn Research.
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