[PCB_FORUM] Re: 16.3 Constraint Manager question (Added Images)

  • From: Mark Salberg <msalberg@xxxxxxxxxxxx>
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Mon, 11 Apr 2011 06:54:43 -0400

Hi Jean, I do use electrical_constraint_set in schematic to create a Cset and assign Cset to a net as well. I use things like 50_ohm_imp, xtalk etc. Also use differential_pair property which works great too. But I would be very interested in details how to use it for ML group. Cadence rep told me that it is better to assign in Allegro CM, but would rather assign in Concept.


I would think that this would assign a elec Cset to the nets assigned, the also create a ECset of the name entered in the Value field.
It does not over write delta / tol or change any targets as I was getting?

Thanks for your reply!

Mark

On 4/18/2011 6:47 AM, TEYSSIER Jean-Charles wrote:

Hi Mark,

I use electrical_constraint_set for this kind of purpose : one constraint set by match group.

/Jean-Charles TEYSSIER /

------------------------------------------------------------------------

*De :*icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] *De la part de* Mark Salberg
*Envoyé :* lundi 18 avril 2011 12:44
*À :* icu-pcb-forum@xxxxxxxxxxxxx
*Objet :* [PCB_FORUM] Re: 16.3 Constraint Manager question (Added Images)

Hi all,
I found that you can not use the Rel Prop delay property in Concept HDL schematic. I was only entering a Matched Length Group name as a value. Which it then created a ML group in Allro CM of that name, but would over write with default settings every time I packaged. I would have to incorporate a host of syntax / variables in the value field. Not intuitive at all! So, guess I am forced to create the ML group "Manually" in Allegro CM, then manually add all nets / xnets in that group. Also losing the added benefit to see the properties in the schematic.

This came straight from Cadence.

Mark

On 4/17/2011 4:28 AM, O Migs wrote:

Hi Mark,

Just a thought. Do you have "Create user-defined properties" selected during the netin process? This option allows the creation of property definitions from the netlist.

Best regards,

-oscar

On Thu, Apr 14, 2011 at 3:46 AM, Mark Salberg <msalberg@xxxxxxxxxxxx <mailto:msalberg@xxxxxxxxxxxx>> wrote:

Here is the same as original message WITH images.

I was wondering if anyone there has run into this one?

After adding Prop delay property on nets in schematic (Concept), package to Allegro, all nets are assigned to a Matched Length group in CM.

Set target, add delta / tolerance and assign pin pairs as Longest Pin Pair. _Everything is fine until packaging schematic changes to Allegro next time!_
*After packaging*, the delta / tolerance is defaulted back to *0 mil:5%???
Thus causing all Prop delays to fail.
*
Any Ideas?
I just finished a design using this method, but it never did this.

P.S. I really like the idea of assigning in the schematic.

Thanks in advance,
Mark

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