[ibis] Re: IV-VT Mismatch

  • From: "Tom Dagostino" <tom@xxxxxxxxxxxxxxxxx>
  • To: <pankaj26492@xxxxxxxxx>, <ibis@xxxxxxxxxxxxx>
  • Date: Fri, 30 Oct 2015 09:45:47 -0700


There are multiple reasons why you can have these end point issues. Poorly
extracted IV curves, poorly extracted VT curves, the wrong test load
resistance, poor model making, extracting the VT and IV curves at different
settings, etc. The model maker should not release a model that has not been
passed through the IBIS Golden Parser which would show up this and other issues.

I’ve evaluated hundreds of models made by others and it amazes me at times what
I see in them; 1 psec risetimes from a serial interface output, 10E300 amps of
current in a power clamp, min/typ/max corners done at 1.71/3.3/5.5V, VT curves
in an input model, pins without models assigned to them, etc.

Without more detail it is impossible to give you an answer other than VT curves
not limited points, etc. Was this model created from SPICE simulations,
measurements, do the IV curves look reasonable for the technology used in the
buffer, do the VT curves have reasonable rise and fall times for the type of
buffer modeled, etc.


Tom Dagostino



Teraspeed Labs

From: ibis-bounce@xxxxxxxxxxxxx [mailto:ibis-bounce@xxxxxxxxxxxxx] On Behalf Of
pankaj gupta
Sent: Thursday, October 29, 2015 10:00 PM
To: ibis@xxxxxxxxxxxxx
Subject: [ibis] IV-VT Mismatch

I am fully aware about how tool checks for IV-VT mismatch or what is IV-VT
mismatch but why IV-VT mismatches are happening. Please don't say data limited
point or other things mentioned in cookbook.


Pankaj Gupta

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