EPEPS 2017 IBIS Summit
Agenda
Please join us for the free IBIS summit at EPEPS 2017 in San Jose,
California next week!
Registration information is at the bottom. Presentation materials will be
available on-line during the event.
Many thanks to our co-sponsors listed below.
Mike LaBonte, SiSoft
Chair, IBIS Open Forum
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IBIS Summit at EPEPS 2017
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IBIS SUMMIT:
October 18, 2017 13:00-18:00
LOCATION:
DoubleTree by Hilton Hotel
2050 Gateway Place
San Jose, California
ROOM:
Monterey
SPONSORS:
IEEE EPEPS
Keysight Technologies
Synopsys
EPEPS:
26th Conference on EPEPS 2017 <http://www.epeps.org/>
(Electrical Performance of Electronic Packaging and Systems)
DATES:
Sunday-Wednesday, October 15-18, 2017
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AGENDA (Order and times subject to change)
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13:00
REFRESHMENTS & SIGN IN
13:10
OFFICIAL OPENING
* Welcome to Summit
* Introductions
Bob Ross, Teraspeed Labs
13:15
Go Big or Go Home: The First Transatlantic Telegraph Cable and the Birth
of Electrical Engineering
Thomas Lee, Stanford University
14:00
IBIS Update
Mike LaBonte, SiSoft
[Presented by Bob Ross, Teraspeed Labs]
14:30
IBIS-AMI Modeling Using Scripts and Spice Models
Wei-hsing Huang, SPISim
15:00
[TBD: equalization with PAM4 topic]
Nana Dikhaminjia, Ilia State University
15:30
BREAK, REFRESHMENTS (15 Minutes)
15:45
Interconnect Modeling Using IBIS-ISS and Touchstone
Michael Mirmak (Intel Corporation)
[Presented by Bob Ross, Teraspeed Labs]
16:20
Interconnect Modeling: New Features for Rail Connections
Bob Ross, Teraspeed Labs
16:50
OPEN DISCUSSION and CLOSING REMARKS
16:50
CLOSING REMARKS
Bob Ross, Teraspeed Labs
17:00
END OF MEETING
Next Open Forum Meeting: October 26, 2017
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Those involved in IBIS Model development, EDA tool development, and
digital circuit design are invited to participate. If you want to
participate, please register with the information below:
Name:
E-mail address:
Company:
Send to:
Mike LaBonte (mlabonte@xxxxxxxxxx <mailto:mlabonte@xxxxxxxxxx> )
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