[ibis-macro] Re: upcoming Verilog-AMS LRM change impacts array syntax

  • From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
  • To: <kwillis@xxxxxxxxxxx>, <ibis-macro@xxxxxxxxxxxxx>
  • Date: Tue, 29 Nov 2005 13:35:26 -0800

Maybe we could define a (Verilog-AMS) macro which
is an empty text for previous versions and a back
tick for the newer versions:
 
'ifdef __VAMS_LRM2.3 
   `define BackTick `
`else 
   `define BackTick
`endif 

    I_pc[1:IVpc_length] = `BackTick{ 0.08,  0.00,  0.00,  0.00},  
 
This needs to be tested, though, I am not sure
if it will work...
 
Arpad
=================================================
 
 


________________________________

From: Muranyi, Arpad 
Sent: Tuesday, November 29, 2005 1:28 PM
To: 'kwillis@xxxxxxxxxxx'; ibis-macro@xxxxxxxxxxxxx
Subject: RE: [ibis-macro] upcoming Verilog-AMS LRM change impacts array syntax


Ken,
 
Not a bad idea, except that it would duplicate all
of the data, which can become ugly if you have 1000
point Vt tables...  Is there a better way to do it?
 
Arpad
===================================================

________________________________

From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] 
On Behalf Of Ken Willis
Sent: Tuesday, November 29, 2005 1:25 PM
To: ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] upcoming Verilog-AMS LRM change impacts array syntax



Hi, 

I got the information from our Spectre team that the array syntax will change 
in the next release of 
Verilog-AMS LRM (version 2.3), likely in 2h06. For example in the IBIS_OpenSink 
model you have: 

  parameter real 
    I_pc[1:IVpc_length] = { 0.08,  0.00,  0.00,  0.00}, 
    V_pc[1:IVpc_length] = {-5.00, -1.00,  5.00, 10.00}, 
    I_pd[1:IVpd_length] = {-0.10,  0.00,  0.10,  0.20}, 
    V_pd[1:IVpd_length] = {-5.00,  0.00,  5.00, 10.00}, 
    I_gc[1:IVgc_length] = {-0.08,  0.00,  0.00,  0.00}, 
    V_gc[1:IVgc_length] = {-5.00, -1.00,  5.00, 10.00}; 

The syntax will be changed from: 

{-5.00, -1.00,  5.00, 10.00}; 
to 
'{-5.00, -1.00,  5.00, 10.00}; 

With the backtick added. This is being done to comply with SystemVerilog. 

One suggestion was to consider supporting a macro so that the building blocks 
would work with LRM2.2 compliant simulators and LRM2.3 compliant simulations, 
for example: 

e.g; 
'ifdef __VAMS_LRM2.3 
  parameter real 
    I_pc[1:IVpc_length] = '{ 0.08,  0.00,  0.00,  0.00}, 
    V_pc[1:IVpc_length] = '{-5.00, -1.00,  5.00, 10.00}, 
    I_pd[1:IVpd_length] = '{-0.10,  0.00,  0.10,  0.20}, 
    V_pd[1:IVpd_length] = '{-5.00,  0.00,  5.00, 10.00}, 
    I_gc[1:IVgc_length] = '{-0.08,  0.00,  0.00,  0.00}, 
    V_gc[1:IVgc_length] = '{-5.00, -1.00,  5.00, 10.00}; 
`else 
  parameter real 
    I_pc[1:IVpc_length] = { 0.08,  0.00,  0.00,  0.00}, 
    V_pc[1:IVpc_length] = {-5.00, -1.00,  5.00, 10.00}, 
    I_pd[1:IVpd_length] = {-0.10,  0.00,  0.10,  0.20}, 
    V_pd[1:IVpd_length] = {-5.00,  0.00,  5.00, 10.00}, 
    I_gc[1:IVgc_length] = {-0.08,  0.00,  0.00,  0.00}, 
    V_gc[1:IVgc_length] = {-5.00, -1.00,  5.00, 10.00}; 
`endif 

Something to think about. 

thanks, 

Ken Willis 
Cadence Design Systems 
270 Billerica Road 
Chelmsford, MA 01824 
(978) 262-6540 

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