Minutes from 2 aug 2005 ibis-macro phone call are attached. Note that we have the ongoing AR to read the Verilog-AMS LRM: http://www.sisoft.com/ibis-macro/docs/verilog_ams_lrm_2.2.pdf Mike
meeting date: 2 aug 2005 attending: Arpad Muranyi, Ken Willis, Mike LaBonte, Barry Katz, Todd Westerhoff AR Review: - AR: Ken will send some Cadence macros Done, uploaded to website. - AR: Mike will change email list so that reply is to sender Done - AR: All look into http://accellera.org Wrong! We were supposed to read the LRM. See AR below. Letter responses - Fred Balistreri and Ian Dodd added to reflector. Andrew Ingraham added himself. - C.K. Kumar no longer at Synopsys, Geoffrey Ying named. AR: Arpad will send letter to Geoffrey Ying @ synopsys LRM discussion - Arpad has had continued discussions with Verilog-AMS discussion group. - Verilog-AMS reflector members may not understand how much variation there is among SPICE implementations. - Is there an archive of these discussions? AR: Arpad will send reflector info AR: All read verilog-AMS LRM: http://www.sisoft.com/ibis-macro/docs/verilog_ams_lrm_2.2.pdf Plan for DesignCon: - 4 phone calls left - Make enough library elements to implement pre-emphasis buffer - Demonstrate it in AMS - Barry can translate AMS example to ISPICE4 (if simple enough) - Demonstrate it in DML - Does Cadence example need cleanup? Discussion of Cadence pre-emphasis DML model - Looks "non-standard", do we need all these features? - Seems like it could be simplified, flattened - Should use separate IBIS buffers - Arpad's pre-emphasis example already does this - Best way to handle C_comp? - If set to 0 in 2nd tap, slight error will be introduced. - Could set C_comp proportional to each buffer size - Best method is to extract each tap separately - Should we use Ramp-only buffers? Maybe, maybe not. AR: Arpad will convert his pre-emphasis buffer example to use building blocks based on Mike's skeleton library Next meeting: Tuesday August 9, 2005.