[ibis-macro] ibis-macro 27 oct 2005 meeting minutes
- From: "Mike LaBonte (milabont)" <milabont@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Thu, 29 Sep 2005 16:59:06 -0400
Minutes attached. ARs from the last phone call:
AR: Ken get List of Cadence/Telian customers willing to try it
AR: All review library for completeness
AR: Mike will annotate library modules
Mike
meeting date: 27 sep 2005
attending: Arpad Muranyi, Todd Westerhoff, Ian Dodd, Bob Ross,
Ken Willis, Mike LaBonte
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Review of ARs:
None recorded, but actually:
AR: Mike will annotate library modules
- TBD
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Review of DesignCon East IBIS summit:
- Presentation went well
How do we get people to try it?:
- Wrap it up in a kit
- Looking for semiconductor vendor
- If we ask vendors to make templates, they will try to
out-wait each other
- EDA companies want to see demand
- Maybe Cisco can get a vendor to produce one
- Can Intel produce one?
- Arpad is already putting a lot of time into it
- Not a big proponent of macro-model approach
- Would rather write direct AMS models
- Maybe could do one
- Have something in VHDL now, but would have to convert for macromodel
- Ian: Macromodel structure layer may not be necessary
- Vendors may not be ready
- Todd: easier to learn macromodels
- Todd: this is for vendor model developers
- Ian: SI engineers need to cobble together models before getting
the real thing
- Put templates in the tools and tell customers to modify
as needed?
- No, the benefit is when data comes from IC vendors
- Are IC vendors supplying VHDL now?
- patchy
- A Mentor VHDL rep is trying to convince IC vendors
- IBIS would not have taken off if not for s2ibis
- Quad also had spi2mod, for example
- Are EDA companies waiting for a substitution tool?
- The awareness isn't there at all yet
- Would an FPGA company be more willing?
- They want to interface to everbody
- They have buffers that IBIS can't model
- We have no EDA vendor conversion tools yet
- Do we have to write the first one?
- Synopsys may support it
- 2005.09 IBIS 4.1 support
- Need to provide library in both Verilog and VHDL
- Arpad will write them completely in VHDL, take verilog only
as far as possible
- IBIS buffer is the stumbling block
- How compatible do they need to be?
- Customers need to use it
- Problem: buffer instance data can't be passed to definition in verilog
- Arpad: tables could be passed in
- If it's clunky IC vendors will frown on it
- Better to use simple syntax and conversion scripts
- Does [Driver Schedule] make pre-emphasis example seem trivial?
- Need advertising
- Tool vendors
- Users
Is the building block library stable?
- no
- Can't really promote this until it is
AR: Ken get List of Cadence/Telian customers willing to try it
AR: All review library for completeness
AR: Mike will annotate library modules
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Next meeting: Tuesday 5 oct 2005.
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