All,
BIRD189.5_draft15_v5 is attached per discussion about some unaddressed
comments in the rail section listed below.
Bob
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Bob Ross
Sent: Thursday, January 11, 2018 5:12 PM
To: ibis-interconn@xxxxxxxxxxxxx
Subject: [ibis-interconn] Re: My comments on RE: Re: BIRD189.5_draft15_v4
All,
Thank you for the comments. BIRD189.5_draft15_v4.docx responds to most of
them.
I tried to change all red text to black.
I used Interconnect Model instead of model for clarity. Technically we
should state that they not inside the Interconnect Model Group, but are
referenced by the Interconnect Model Group. I did not make this change.
Also I did not make any changes related to the comment below. Because we
are discussing Rail terminal connections for different Interconnect Models,
and we have a set of allowable terminals at each interface, we need to be
clear what is allowed at each interface.
The first paragraph on page 7 gives the forward reference to the statement
details below.
Page 8 The following are not rules
o At the pin interface, Pin_Rail terminals can be identified by pin_name,
signal_name or bus_label entries. An external pin_name maps directly into a
Pin_Rail pin_name entry or the pin_name can be mapped into a bus_label or
signal_name terminal with the information given in the [Pin] keyword above
or by the [Pin Mapping], [Bus Label], or [Die Supply Pads] keywords
described later in this section.
o If a die pad interface is used, the Pad_Rail terminal can be identified
by pad_name, signal_name or bus_label entries. Connections between die pad
interfaces in two different Interconnect models can be made by using
identical terminal names or identifying the common bus_label or signal_name
information that is available in the [Pin], [Pin Mapping], [Die Supply
Pads], or [Bus Label] keywords.
o At the buffer interface, Buffer_Rail terminal can be identified by
signal_name or bus_label entries or directly by the *_ref entries that are
associated with Buffer_I/O pin_names.
o An Interconnect Model with only rail terminals (no I/O terminals) can
be used for a Power Delivery Network (PDN).
o A PDN structure can also exist in an Interconnect Model with I/O
terminals.
o Also, rail terminals or A_gnd can be used in Interconnect Models to
provide reference node for the electrical interconnections associated with
*_I/O terminals.
Is this not already covered in the paragraph on the top of page 7:
The remaining terminals are used for POWER or GND and are referred to as
rails. The rail identifiers are pin_name, signal_name, bus_label
(described below) and pad_name entries (described below) according the the
allowable association rules summarized in Section XXX (Connecting Pins, Pads
and Buffer Terminals) and Table 41.
Bob
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Wednesday, January 10, 2018 10:01 AM
To: ibis-interconn@xxxxxxxxxxxxx
Subject: [ibis-interconn] My comments on RE: Re: BIRD189.5_draft15_v3
All,
Specific comments on this version:
All else is good.
Walter
Page 5 Make the following black
Terminal_type A_gnd is added to connect a terminal to the EDA tools ground
(or node 0 or equivalent) at any interface.
More statements are given to show how bus_label names can be entered with
any or all of the [Pin Mapping], [Pin], [Bus Label] and [Die Supply Pads]
keywords
Page 6 In addition some à In addition, some
Page 8 The following are not rules
o At the pin interface, Pin_Rail terminals can be identified by pin_name,
signal_name or bus_label entries. An external pin_name maps directly into a
Pin_Rail pin_name entry or the pin_name can be mapped into a bus_label or
signal_name terminal with the information given in the [Pin] keyword above
or by the [Pin Mapping], [Bus Label], or [Die Supply Pads] keywords
described later in this section.
o If a die pad interface is used, the Pad_Rail terminal can be identified
by pad_name, signal_name or bus_label entries. Connections between die pad
interfaces in two different Interconnect models can be made by using
identical terminal names or identifying the common bus_label or signal_name
information that is available in the [Pin], [Pin Mapping], [Die Supply
Pads], or [Bus Label] keywords.
o At the buffer interface, Buffer_Rail terminal can be identified by
signal_name or bus_label entries or directly by the *_ref entries that are
associated with Buffer_I/O pin_names.
o An Interconnect Model with only rail terminals (no I/O terminals) can
be used for a Power Delivery Network (PDN).
o A PDN structure can also exist in an Interconnect Model with I/O
terminals.
o Also, rail terminals or A_gnd can be used in Interconnect Models to
provide reference node for the electrical interconnections associated with
*_I/O terminals.
Is this not already covered in the paragraph on the top of page 7:
The remaining terminals are used for POWER or GND and are referred to as
rails. The rail identifiers are pin_name, signal_name, bus_label
(described below) and pad_name entries (described below) according the the
allowable association rules summarized in Section XXX (Connecting Pins, Pads
and Buffer Terminals) and Table 41.
Page 9 Change
If an *_I/O pin_name has terminals in the Interconnect Model Group with the
interface combinations: pin to buffer, or pin to die pad and die pad to
buffer, then the Interconnect Model(s) in the Interconnect Model Group
define the full interconnect electrical path between the pin and buffer
interfaces. If this is not he case then:
To
If an *_I/O pin_name has terminals in a model in the Interconnect Model
Group with the interface combinations: pin to buffer, or pin to die pad and
die pad to buffer, then the Interconnect Model(s) in the Interconnect Model
Group define the full interconnect electrical path between the pin and
buffer interfaces. If this is not the case then:
Page 9 Change
If a PDN structure has terminals in the Interconnect Model Group with the
interface combinations: pin to buffer, or pin to die pad and die pad to
buffer, then the Interconnect Model(s) in the Interconnect Model Group
define the full PDN electrical path between the pin and buffer interfaces.
If this is not he case then:
To
If a PDN structure has terminals in a model in the Interconnect Model Group
with the interface combinations: pin to buffer, or pin to die pad and die
pad to buffer, then the Interconnect Model(s) in the Interconnect Model
Group define the full PDN electrical path between the pin and buffer
interfaces. If this is not the case then:
Page 13 Change text from Red to Black
Page 27 Change the following from Red to Black
The IBIS-ISS subcircuit terminals shall not contain the ideal ground node
(node 0 or its synonyms).
Page 27 accept Radeks comments and change
For Touchstone files, each unused port and its corresponding Terminal_number
may be terminated by the EDA tool in simulation with a resistor whose value
corresponds to the Unused_port_termination subparameter entry. The resistor
is connected to the models reference terminal.
To
For Touchstone files, each unused port and its corresponding Terminal_number
shall be terminated in simulations with a resistor whose value corresponds
to the Unused_port_termination subparameter entry. The resistor is connected
to the models reference terminal.
Walter Katz
wkatz@xxxxxxxxxx
978.461-0449 x 133
Mobile 303.335-6156
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Mike LaBonte
Sent: Wednesday, January 10, 2018 12:20 PM
To: ibis-interconn@xxxxxxxxxxxxx
Subject: [ibis-interconn] Re: BIRD189.5_draft15_v3
Thanks Bob. The attached document has exactly the same text as the document
sent by Bob, but the markup has been regenerated using draft 14 as the
baseline. It may be slightly easier to read in some places.
Mike
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Bob Ross
Sent: Wednesday, January 10, 2018 12:14 PM
To: ibis-interconn@xxxxxxxxxxxxx
Subject: [ibis-interconn] BIRD189.5_draft15_v3
All,
For review and with changes made at the January 10, 2018 meeting.
I changed or corrected the I/O pin section bullet indentations.
Mike may generate a comparison version with draft14.
Bob
--
Bob Ross
Teraspeed Labs
www.teraspeedlabs.com <http://www.teraspeedlabs.com/>
bob@xxxxxxxxxxxxxxxxx
Direct: 503-246-8048
Office: 971-279-5325
Attachment:
bird189.5_draft15_v5.docx
Description: application/vnd.openxmlformats-officedocument.wordprocessingml.document
