Walter,
I will let Randy confirm this because I only glanced over that data sheet, but
my
understanding of VREFCA is that it is a pin to which a non-zero voltage (Vdd/2)
is
applied. Look at note #2 on pg. 9, which says:
2. VREFCA = VDD/2, VDD at valid level.
I think this is a pin to which the negative terminal of a bunch of differential
receivers
are connected to inside the component. This is what "A_extref" and Ext_ref was
invented for in IBIS.
Now, given its name, in what sense is this a "reference" pin, since it is
supposed have
a non-zero voltage? And, if it has a non-zero voltage, with respect to what
"other
reference" is its voltage measured? Is there such a thing as a "true" or
"ultimate"
reference? If so, what makes such a reference "true" or "ultimate"?
Also, does a reference pin supposed to have a pure DC voltage? This pin might
actually have a lot of noise on it (if it is not decoupled properly from
crosstalk and/or
other noises sources)... Can a reference really be a reference if it not only
has a DC
voltage but also noise on top of that? From the perspective of the
differential inputs
which use this reference pin, none of that matters. They will simply "report"
whether
their signal input is higher or lower than this reference input, regardless of
what the
DC voltage is and how much noise is on top of that (within the operating
limits).
So from the perspective of the differential input stage, this pin is indeed a
reference
pin.
I would dare to say that an ultimate (or true) reference has NO voltage, because
we can't measure it, i.e. there is no other reference available to measure it.
Kind
of like asking the question: What is the voltage of planet Earth? We can't
measure
it, unless we measure it with respect to another planet or the Sun or some place
in the Universe (if we can)... But the decision of what this ultimate
reference is,
or where it is, is an arbitrary choice (ignoring any physical limitations in our
measurement equipment). It is up to us to decide whether we consider that to be
on the Sun, on the Earth, or in the lab of my house. I could declare that this
"ultimate
reference" is on my computer's motherboard, if I don't care about how the
voltages
of its power supply terminals are related to anything else around it. Another
name
for this ultimate reference is "floating ground". The Earth may be a floating
ground
with respect to the Sun. So could be the power supply terminals of my
motherboard
in my lab, if I don't connect it to the green (ground) wire in the
three-pronged outlet
in my wall.
I believe this is what the SPICE Node 0 is all about, everything is measured
with
respect to it (directly or indirectly), but Node 0 by itself has NO voltage,
because
there is no other reference to which a voltage could be measured. Node 0 is the
"ultimate reference" in the SPICE world. This is why I think Bob is incorrect
when
he says "Node 0 has a zero point zero volt voltage". (With respect to what, if
it
has no reference?)
This implies a relativity of some sort. My house ground may be a global
reference
for all the projects I do in my lab if I don't care about what is going on
outside my
house. But the same house ground might be only a local reference if I do care
about
what is going between the computer in my house and my neighbor's house.
Similarly,
A_gnd may be defined as a local reference for a [Component] in a design where
multiple [Components] are present, in which case there would be another "more
global" reference than them to be able to say what the voltage relationships are
between each of those local A_gnd references. But the same local A_gnd
reference
might also be used as if it was a global reference for all measurements inside
that
one [Component] if I never ask the question what is the voltage of that A_gnd.
Going deeper, A_gnd might be defined as a local reference for the [Model]s in
the IBIS [Component], but if I am only interested in the voltages within a
single
[Model], this local reference might be used as if it was a global reference
within
that [Model].
And you are right, if we want, we can model the "stuff" that goes between these
different local references to see what their voltage relationships are when the
stuff that is between them is non-ideal. But if we are not interested in
seeing what
the non-deal nature of that stuff is, we can just short them together with an
ideal
short, essentially "elevating" all these local references to a higher level, to
either
act as a broader local reference, or perhaps elevate them to the "ultimate
reference"
status if they were a global reference.
So if we accept the definition that a global reference is global because there
is no
other reference available to measure its voltage, then I would say that the
difference
between a local and global reference is that a local reference can and will
have a
voltage (with respect to the global reference), while a global reference will
not
and CANNOT have a voltage. Also, a local reference may have any voltage, it is
not restricted to zero volts, or DC only. Regardless of what its voltage is and
whether it is fluctuating or not, the point is that anything that uses it as a
reference will have a voltage value with respect to it.
Consequently, a Vcc or Vdd pin may be used as a reference just as well as a Vss
or
Vssq pin, or the dreaded GND pin. Even your "beloved" ECL negative supply pin
(Vee) or the negative supply pin of RS232 buffers (-Vcc) may be considered a
reference. Any of them can be defined as a local reference, or a global
reference.
The beauty of all this is that by connecting any of the local references to the
global reference, they will act as if they were the global reference.
But we have to be careful about what we call a reference node and the voltage of
that reference node. Based on the above discussion, only local references
(nodes)
can have a voltage.
The famous example for that is the IBIS [*** Reference] keywords. We have
discussed them in the past. I think of them as a definition of a reference
terminal
(node) for the [Model]. The voltage value that they are associated with are
with
respect to another reference, which in my mind is the global SPICE reference,
Node 0. So if the [Pulldown Reference] or [Ground Clamp Reference] keywords
are assigned 0 volts, that means that they are 0 volts away from the SPICE Node 0
global reference. But I would consider each of these keywords as a definition
for
a node, which should be treated as a local reference for each [Model] (if they
are
not shorted together by an ideal short or bus). Our famous "Vcc relative" I-V
curves are an example for that, because their origin (reference) are the
[Pullup
Reference] and [POWER Clamp Reference] terminals. While we fixed the C_comp
referencing problem relatively early on, we still didn't fix the related
problem with
Vinh, Vinl and related measurement parameters. As far as I am concerned, they
should all be referenced to one of the [*** Reference] keywords, not the global
SPICE reference Node 0 to facilitate power aware simulations, but that
discussion
is for another day.
Now, going back to the Micron data sheet you brought up as an example,
* VREFCA
* VSS
* VSSQ
I don't think Vrefca would be connected together with Vss and Vssq (since I
think
they have different voltages) but I think that it is certainly possible to
connect the
Vss and Vssq pins/balls together on the board. Since they are most likely
routed
independently in the package and on-die interconnect from the pin/ball towards
the buffer, we will want to have independent local references for each [Model].
For
this reason, the buffer terminals defined by the [*** Reference] keywords should
be kept local for each buffer [Model] (or group of [Model]s connected to Vss and
Vssq). That is absolutely necessary, since the I-V curves are all connected
between
these [*** Reference] nodes and the signal terminal of the [Model]. But what
should we do for BIRD158 buffer [Model]s in which we are not using these
[*** Reference] buffer terminals at all? If we want to use A_gnd for them, what
is the reason to keep an independent local A_gnd for each [Model] when these
types of buffer models are not intended to be used for power aware simulations,
i.e. the noise on the [*** Reference] nodes are irrelevant, even if the power
lines
have detailed interconnect models?
Now let's turn to the interconnect models. First, let's consider a BIRD158
buffer
model with a simplification so that it is reduced to a simple Thevenin circuit.
In
that arrangement, the negative terminal of the voltage source is connected to
the local reference (A_gnd), the positive terminal is driving a series resistor
which
is connected to the buffer's signal terminal (pad). Consider that this
[Component]
has two pins and pads for the signal and Vss. (We can do without a Vdd pin,
since
the Thevenin driver model is not using Vdd). The package model consist of two
single conductor W-elements to describe the non-ideal nature of the signal and
Vss traces between the pins and pads. As we all know, in addition to the
conductor
terminals, the W-element also has at least one reference terminal.
I know how to connect the Thevenin resistor to the signal W-element. But I
wonder
how would you connect the local reference of the Thevenin voltage source (A_gnd)
with the package model's W-elements. Would you connect it together with the
reference terminal of the signal's W-element, or the conductor terminal of the
W-element that is there for the Vss pin/pad? The same question can be raised
when the two single conductor W-elements are replaced by a two-conductor
W-element, or a 4-port Touchtone model. The same questions could also be
asked with the variation on how many reference terminals the W-element or
Touchstone model has. One for each of their "conductors" (ports), N+1 or more
(N+2, or 2N)? And how would we do the same with conventional (I-V curve
based) models, where we can support power aware simulations, i.e. the buffers
powered through the [*** Reference] terminals. And how would we do all this
when there are multiple [Model]s present in the [Component], when each of
them (or at least a few groups of them) have different local references?
I don't want to go through the pros and cons of each of these options, because
it
will make this already long email even longer. But these are the questions we
need to keep in mind when we are making our decisions on how to properly define
our references.
Sorry for the long email, but I did it with the intent to help us find a useful
solution
for our Earth shattering ground problems...
Thanks,
Arpad
====================================================================
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Thursday, March 15, 2018 7:20 AM
To: IBIS-Interconnect <ibis-interconn@xxxxxxxxxxxxx>; IBIS-ATM
<ibis-macro@xxxxxxxxxxxxx>
Subject: [ibis-interconn] Re: Another stab at defining A_gnd
Arpad,
Making assumption that "making A_gnd a local reference for a [Component]. " has
the following problems.
* The example below has three local reference nodes:
* VREFCA
* VSS
* VSSQ
* I suspect these three are connected together to a single supply CAD net
(e.g. Vref) on the Board
* Note that I use the word CAD net not node, since the power
distribution model on the board, package and die for this supply net can be
distributed with different nodes at different buffers. This is the concept of
bus_lables that represent a single node for multiple buffers.
* For this memory chip, I expect Micron would want to deliver a power aware
coupled model that includes DQ and DQS, and they have a single reference net
(Signal name VSSQ).
* For the controller, Intel might want to deliver a full coupled model with
DQ, DQS and Address Command (ADDCMD) signals that go with. Intel likely may
also have isolated the "reference nets" (Intel and Micron will likely call this
isolating the "grounds"). Passing in A_gnd to this circuit will not allow the
interconnect for the DQ, DQS signals to use a different reference than the
ADDCMD signals.
Making A_gnd a local reference node for either a Model or Component has its
problems. I am leaning to saying A_gnd is an alias for Node 0 (or simulator
node), and stating that A_gnd as a terminal name, or using Node 0 in subckts
should be discouraged if the model needs to support Power Aware simulations
that are not "Ground Based" power aware simulations.
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
978.461-0449 x 133
Mobile 303.335-6156
From:
ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
<ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>>
On Behalf Of Muranyi, Arpad
Sent: Wednesday, March 14, 2018 11:06 PM
To: IBIS-Interconnect
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>; IBIS-ATM
<ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>
Subject: [ibis-interconn] Re: Another stab at defining A_gnd
Walter,
I think we in "violent agreement". In fact I started to write the same
illustration, using a W-element
and a resistor in my previous reply, but I deleted it because it was getting
too long...
The point I was trying to make is that this word "reference" is sometimes over
used, abused... We often
give it a mysterious, special meaning. But in reality there is really nothing
special about it. It is simply
a node name that is designated for the purpose of voltage measurements.
Whether it is global or
local, or whether it is ground or any other "general purpose" node, doesn't
matter, as long as the
voltage measurements make sense. This is why I was "sensitized" to your usage
of this word in your
text on which I was commenting.
Anyway, that text needs some work. But before we get into that, we need to
agree on the concepts.
Especially after today's Interconnect Meeting. I wonder now what we think
A_gnd is. Is it a local
reference to [Model], to [Component], or what? Or, is it a global reference,
and if so, is it Node 0, or
just a global node name that could be anything other than Node 0? I don't
think we gave an answer
to these questions today, although Mike started to make changes in the BIRD
draft along these lines.
This question about [Model] vs [Component] is bugging my mind now. If it is a
local reference to
[Model], we could have a [Component] with many [Model]s which all have their
own, independent
references. How would that work if several of these [Model]s are connected to
the same package
model that has a single reference? We might have a problem if the different
[Model] references
are connected to different voltages. For this reason I am leaning towards
making A_gnd a local
reference for a [Component]. That seems to be safe, because one package
cannot serve multiple
[Component]s, so all of the buffers and package models within a [Component]
could safely be
referenced to the same local reference node.
Thanks,
Arpad
=============================================================================
From:
ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Wednesday, March 14, 2018 10:00 AM
To: IBIS-Interconnect
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>; IBIS-ATM
<ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>
Subject: [ibis-interconn] Re: Another stab at defining A_gnd
Arpad,
Does not matter if some of this text is in IBIS or an introduction to the BIRD
which clarifies A_gnd as a local reference. The bottom line is IBIS describes
electronically what is in a Data Book, and possibly additional information that
is not in a Data Book that is necessary to do sufficiently accurate
simulations. I am enclosing the Data Sheet for a part I downloaded from the
Micron site.
The table on page six lists the signal names that are reference pins for:
VREFCA Supply Reference voltage for control, command, and address
pins.
VSS Supply Ground.
VSSQ Supply DQ ground.
Your comment
A somewhat more general, but still technical issue I have (especially in the
context of SPICE
elements) is that you talk about ***reference*** too much. Take, for example,
a resistor.
It has two terminals. Why do we need to call its "other terminal" ***the***
reference?
Just confuses the issue. We are using the word "reference" to mean two
different things. When reporting a "voltage" in a measurement or a simulator it
must be measured between two point. One can report the voltage between the two
ends of a resistor, or one can report the voltage at each end of a resistor to
a local "A_gnd", or to a simulator reference node. This is the first meaning of
reference. There is no current flowing from the resistor to A_gnd or the
simulator reference node. Now replace the resistor with a trace on a PCB, and
we want to measure the voltage at both ends of the trace. There is no
difference between making these measurements in the lab and in a simulation.
There is a difference between a resistor and a W-Line representation of that
trace.
Both the resistor and the trace have current flowing through them. The Tx is
sending electrons down the line, how do they get back? Different simulators
make different assumptions about this. Some assume ideal "return paths" for
these electrons to get back to the Tx, or in particular the rail voltage
sources that supply the electrons to the Tx in the first place. Other
simulators may account for the details of how these currents are returned. I
suspect that Scott, Brad, Radek and I will not be able to agree on how this
should be done. I believe that Scott, Brad, Radek and I can agree that we can
write interconnect models according to BIRD 189 that will satisfy each of our
own simulator requirements. The problem is that Scott, Brad, Radek and I may
write these models for our own simulators, partly because we do not know what
the requirements are for the other simulators. Scott says using Node 0 as the
reference for all interconnect models is valid ("Ground Reference Simulation").
Brad says no, because the rail interconnect models are different if use the
local reference. At this point all we can ask for is recommendations for how
BIRD 189 models should assign reference terminals. All we can do is to
recommend how a model maker writes models for a component. He may choose to
make his models base on "Ground Reference Simulation", or by using the
recommendations that Brad (or others) may document for us. I think the real
problem is Tx package models, Rx package models, board interconnect models and
connector models can be written with different assumptions. I think it would be
helpful for Brad and others explain the rules that they want followed and what
limitations that they want to impose on the other models in the channel.
How about a trivial case, an package that has 6 terminals, VDD, VSS and I/O at
the buffer and VDD, VSS and I/O at the pin. Inside of the package the two VDD
terminals are connected with a .1 Ohm resistor, the two VSS terminals are
connected with a .1 Ohm resistor, and the two I/O terminals are connected with
a .3" trace that can be represented by a lossy transmission line. What would be
the recommend SPICE subckt for this trivial package?
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
978.461-0449 x 133
Mobile 303.335-6156
From:
ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
<ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>>
On Behalf Of Muranyi, Arpad
Sent: Wednesday, March 14, 2018 3:23 AM
To: 'IBIS-Interconnect'
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>; IBIS-ATM
<ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>
Subject: [ibis-interconn] Re: Another stab at defining A_gnd
Walter,
Thanks for your effort of "stabbing"... :)
This is a good start, but has numerous problems, ranging from small grammatical
ones to
large theoretical (philosophical) ones. I feel it will take quite a bit of
effort to clean it up
and get all of us in an agreement...
My general comments are that talking about IBIS history and how it evolved is
not very
spec-like material. Similarly, making promises about what will be done in
future versions
is quite dangerous. Case in point is the forward looking, unsupported
package/interconnect
model examples associated with Figure 29.
On a more technical side, we all know that a voltage is something that can only
exist between
two locations. Your wording: "pins with a zero voltage" and "buffer rail
voltage" are highly
questionable because in my mind they seem to refer to a single point or
location. How can
we say than that a pin or a buffer rail (by itself) has ***a*** voltage?
Voltage can only exist
between "it" and "something else".
A somewhat more general, but still technical issue I have (especially in the
context of SPICE
elements) is that you talk about ***reference*** too much. Take, for example,
a resistor.
It has two terminals. Why do we need to call its "other terminal" ***the***
reference?
Yes, if we think of the resistor as a one-port, we could consider one of its
terminals the
reference terminal. But how many people think of a resistor as a one-port in a
SPICE
netlist context? How is this different from the W-element or S-element, in
which case
we start talking about ports much more readily? I think this difference comes
from how
these circuit elements are used in the netlist. In the case of W and
S-elements, we are
usually interested in their port voltages, and not the voltage differences
between the
various ports (unless differential signaling comes into the picture). On the
other hand,
in the case of a resistor, what we are interested in depends greatly on how it
is placed
into the circuit. It might be the voltage across it, but it could also be the
voltage between
one or the other of its terminals and something else. I feel that we need a
better definition
for what a reference really is, and when and why we might call a terminal a
reference.
I will stop with this, the rest of the text may depend on how we answer these
questions.
Thanks,
Arpad
=====================================================================
From:
ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Tuesday, March 13, 2018 9:18 PM
To: 'IBIS-Interconnect'
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>; IBIS-ATM
<ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>
Subject: [ibis-interconn] Another stab at defining A_gnd
All,
Here is a discussion and definition of A_gnd based on the presentation and
discussion we had today. I think this could go somewhere in the beginning of
IBIS.
All voltages in IV curve, VT, curves, Measurement Thresholds, Model Spec
voltages in this document are voltage that are either measured in hardware or
simulations reference to an appropriate location in the hardware or node in a
simulation. IBIS originally defined voltage measurements at pins are measured
relative to a reference pin. Data Books usually refer to these reference pins
as "Ground" or supply pins with a zero voltage. As IBIS has evolved to define
rules at the die pad, and with BIRD 189 at the buffer itself it is necessary to
move reference point to the die pad or to the buffer rail voltage. IBIS defines
the reserved name A_gnd to refer to this location.
Note that "measurement" in this document shall either refer to
1. A physical measurement of a voltage between a probe point and a reference
point
2. A simulation "probe" of a voltage between a probed node and a reference
node.
A connection between two or more I/O buffer models can be defined as an
IBIS-ISS netlist which is essentially a list of IBIS-ISS element instances. The
terminals of these elements can reference nodes for the other terminals of
these elements. There is no requirement that the reference A_gnd for one
measurement on a buffer be the same SPICE node as the reference A_gnd for a
measurement at a buffer either in the same component or a buffer in a different
component.
All data in the specification is based on the assumption that rail voltages are
static. [Pin Mapping] allows the EDA tool to determine which pin(s) supply the
voltages to all of the rail terminals of a [Model], and therefore all of the
references for all of the interconnect between [Model]s and pins.
Note that in the case of some ECL, MECL, PECL and RS232, IBIS models may have
voltages that are referenced to some point outside of the component. In this
case the reference location (A_gnd) is external to the component, and the EDA
tool must choose a reference node for rail voltages supplied to the component
and for measurements made at the I/O pin, pad or buffer. This reference "Node
0" is commonly used in this case.
One must take great care in defining reference node connections when doing
Power Aware Simulations. A simulation is a Power Aware Simulation when the rail
voltages referenced to their local reference node or referenced to a simulator
reference node (e.g. Node 0 ) change in time.
Almost every use of the word "ground" in this document refers to a point in the
hardware or a node in a simulation that is the reference for signal and supply
voltage measurements for a Device Under Test. In IBIS 7.0 or 7.1, all of these
reference to "ground" will be clarified to mean the reference point for
measurement (A_gnd).
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
978.461-0449 x 133
Mobile 303.335-6156