[ibis-macro] Re: [ibis-interconn] A question.
- From: "Walter Katz" <wkatz@xxxxxxxxxx>
- To: <ibis-interconn@xxxxxxxxxxxxx>, <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 5 Mar 2013 12:21:46 -0500 (EST)
David,
Please remember that the IBIS [Model] generated according to the IBIS
cookbook is to measure the pullup and pulldown IV curves when Tx is steady
state high and steady state low, and the VT curves of a transitions from
steady state low to steady state high (and steady state high to steady
state low).
THIS NEVER HAPPENS IN A REAL SerDes CHANNEL!!!!!
What does happen on a rising edge that then is steady state high, is the
buffer tries to go to the high state, but before it gets there the first
post cursor tap reduces the drive.
If the rail voltage was 1V, the each side of the Tx transitioned between 0
and 1 V, one would want to generate step responses with each side of the
Tx go through a small voltage swing (e.g. .45-.55 Volts).
Thus the correct way for an IC vendor to describe the analog
characteristics is to describe the analog model of the small signal
transitions. The small signal transition analog model for a legacy IBIS Tx
model is simple linear pullup/pulldown curves (an impedance), a C_Comp,
and a ramp rate. In other words the equivalent analog circuit in OpalT and
BIRD 122. This is another form of surrogate model of the IBIS model. The
IBIS model is iself a surrogate model of the real silicon.
This step will be graphically illustrated in the presentation I have
prepared regarding David's last week's question.
Walter
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of David Banas
Sent: Tuesday, March 05, 2013 11:48 AM
To: 'ibis-interconn@xxxxxxxxxxxxx'; 'ibis-macro@xxxxxxxxxxxxx'
Subject: [ibis-interconn] A question.
Hi all,
I was hoping that you might consider the following question and offer your
comments at today's meeting.
Is the difficulty one runs into, when one attempts to shorten the time
span of IBIS V/T tables, in order to support the bit rates necessary in
modern serial communication design, one of the primary motivators for
including the a.c. behavior of the Tx driver in the Touchstone model of
the on-die interconnect?
Thanks,
David Banas
Sr. Member Technical Staff
Altera <http://www.altera.com/>
+1-408-544-7667 - desk
Did you know Altera offers over 150 free online technical training courses
<http://www.altera.com/servlets/searchcourse?coursetype=Online&WT.mc_id=t9
_ot_mi_mi_tx_a_311> ? Take one today!
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