Scott- We've been using your option A. Mike S. Scott McMorrow wrote:
AllWe are looking at the specification for clock_times and have come across the following problem with these two sentences:The clock times are the times at which clock signal at the output of the clock | recovery loop crosses the logic threshold. It is to be assumed that the | input data signal is sampled at *exactly one half clock period* after a | clock time.I really hate assumptions in specifications since they may be wrong, and are up to interpretation. I believe that the spec really means to define the internal sample point of the sampler, slicer, track hold ... whatever, by having the EDA platform move the delivered clock tick from the clock_times vector by 1/2 a clock period, or UI. If that interpretation is correct then which of the two is correct?1/2 a clock period is defined to be: A) one half of the nominal UI B) one half of the instantaneous UI between two clock samples How is this currently being implemented in currently developed models? regards, Scott -- Scott McMorrow Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 (401) 284-1827 Business (401) 284-1840 Fax http://www.teraspeed.com Teraspeed® is the registered service mark of Teraspeed Consulting Group LLC
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