[ibis-macro] Re: Schematic to discuss in IBIS-ATM re example of Node 0 in interconnect and how they might affect simulations.
- From: "Dmitriev-Zdorov, Vladimir" <vladimir_dmitriev-zdorov@xxxxxxxxxx>
- To: Walter Katz <wkatz@xxxxxxxxxx>, "ibis-interconn@xxxxxxxxxxxxx" <ibis-interconn@xxxxxxxxxxxxx>, IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>
- Date: Wed, 18 Apr 2018 18:29:26 +0000
Walter,
First, let me slightly fix the drawing for W1. Transmission line model W1 is
essentially a two-port object (with two pins on each side) which enforces
current conservation on each side. That is, the currents shown by red arrows
are always equal to each other. Same about those shown by green arrows.
If the reference pins of W1 are connected as below, the "signal" current will
essentially bypass losses in the power rail (R1, R5) etc. Because the current
will mostly circulate in two contours. First contour is signal/PullDown ref of
the driver and port 1 of W1. Second contour is made by the second port of W1,
R2. Some part of the loop current(s) will also go around through capacitors and
the buffers on left and right. But I don't think this is an intention.
Nothing good happens if we connect reference pins of W1 together on either
side, to the left or right from R1/L, or if we place them at the power ref at
the bottom.
[cid:image002.jpg@01D3D710.E2F67E90]
I think what we wanted is to establish the relations between the currents shown
below with 3 arrows, so that the sum of them is kept zero. Unfortunately, this
would be possible if W1 were a single conductor (two pin) object, like resistor
or R/L series connection. But it's not, because this W1 model was created by
considering two conductors, both of them in general being lossy and in an
assumption that there is no return current path for the first conductor of W1
other than the second conductor of W1.
The proper way would be to create not two, but 4-port object from 3 conductors
made by the signal path, power ref, and ground ref paths. Or, if those paths
are non-uniform, use S-parameters instead.
[cid:image004.jpg@01D3D710.E2F67E90]
But if we W1 is given and we cannot change it, we can only make some
assumptions about it. For example, let's assume that it was build considering
ideal "return path". If so, it can be represented by a chain of identical
series RL and grounded GC components, with sufficiently many sections. Also, if
we assume that returned signal current splits equally between power and ground
paths (a weak assumption), we can decide how to build a multi-sectional model
that incorporates losses of this T-line itself, and losses brought by power
distribution network.
In the end, we'd get something like below, but possibly with using many
identical sections, or even converted into a continuous two-conductor 4 port
W-element model.
Of course, many simplifications/different solutions are possible when doing
this, but I don't see a strict way to use W-element model build without PDN
consideration into a design that cares about it.
[cid:image005.jpg@01D3D710.E2F67E90]
Vladimir
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Wednesday, April 18, 2018 10:06 AM
To: ibis-interconn@xxxxxxxxxxxxx; IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>
Subject: [ibis-interconn] Schematic to discuss in IBIS-ATM re example of Node 0
in interconnect and how they might affect simulations.
All,
A picture is worth 1000 words, but it will take more than a 1000 words to
discuss the implications of using Node 0 in interconnect between buffers.
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
978.461-0449 x 133
Mobile 303.335-6156
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- » [ibis-macro] Schematic to discuss in IBIS-ATM re example of Node 0 in interconnect and how they might affect simulations.- Walter Katz
- » [ibis-macro] Re: Schematic to discuss in IBIS-ATM re example of Node 0 in interconnect and how they might affect simulations. - Dmitriev-Zdorov, Vladimir
