[ibis-macro] SPICE compatibility standard library in Verilog-AMS

  • From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
  • To: <ibis-macro@xxxxxxxxxxxxx>
  • Date: Tue, 26 Jul 2005 14:23:53 -0700

I took a little time and read the SPICE compatibility section
of the Verilog-AMS LRM.  This is the summary of what I found.
They know that there is a jungle out there with all the SPICE
flavors.  Therefore they say:
"Verilog-AMS HDL makes no judgement as to which of the various SPICE languages
should be supported. Instead, it states if a simulator which supports 
Verilog-AMS HDL
is also able to read SPICE netlists of a particular flavor, then certain 
objects defined in that
flavor of SPICE netlist can be referenced from within a Verilog-AMS HDL 
In other words, if HSPICE supports Verilog-AMS, you can write
a Verilog-AMS model in which you make all kinds of references
to HSPICE elements in the Verilog-AMS netlist (making that
"Verilog-AMS model" incompatible with any other Verilog-AMS
In order to allow these references, they provide a table of
(element) names which are to be mapped into the SPICE tool's
corresponding native element name, and a port and parameter
list for each (Table E-1).  The problem with this is that in
practice these names become reserved names in Verilog-AMS
and therefore they cannot be used for anything else.  This
is what the message I forwarded earlier was trying to get
rid of.
The author of the message wants these names be removed from
this table, and at the same time he is donating his own SPICE
written in Verilog-AMS library (which I have yet to see how
compatible it is with the 1000's of SPICE flavors).
This is what I am going to try to find out in their next
meeting which is coming up in about 1/2 hour.

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  • » [ibis-macro] SPICE compatibility standard library in Verilog-AMS