[ibis-macro] Pre/de emphasis buffer model
- From: "Paul Fernando" <prfernan@xxxxxxxx>
- To: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- Date: Sun, 15 Jan 2006 18:46:32 -0500 (EST)
Although I initially meant this email for Arpad, I realized that it made more
sense to
mail it to the entire group. Please feel free to comment. Perhaps we could
discuss some
of it during this weeks meeting.
Hi Arpad,
I got the attached file from the sisoft ibis-macro site and simulated it
successfully-
BTW, IT is still checking if we (NCSU) have SP1 (& the newer patch) for hspice
installed.
Could you please check my reasoning in understanding the flow. Perhaps you
could add
comments at the ends of the paragraphs that would aid my understanding.
I can see that the 'PreDeMacro' model instantiates the 'IBIS_IO' model in the
macro
library. This model approximates the IV & VT curves only based on 4 points. In
the
example, the primary & tap1 drivers have the same IV & VT data. So, if I was to
actually
model a 2-tap preemphasis buffer, I would get the IV & VT tables for each tap
and plug
these points in this section (& I would need 2 library models, IBIS_IO_PRIMARY &
IBIS_IO_TAP1). Alternatively, in its updated final state, I'm assuming, we'll
only have
IBIS_IO in the library and the user can select external files that contain the
IV & VT
curves for each tap. Is my understanding correct? Have we reached this point
yet?
Why are 8 'IBIS_CCCS's instantiated? Their net result seems to be nothing since
they
source and sink equal current. If they are used to implement some kind of
scaling, whats
the purpose?
I managed to easily create a 3-tap model and I could see the 3-tap response in
the
awaves, but, like I mentioned earlier, this example used the same IV & VT
points to
describe all the taps, so it is not realistic.
---------------------
When the group mentioned 'creating new templates' did you mean creating basic
files
(like PreDeMacro.va) for DDR, LVDS, multistage buffers etc? Or was it templates
as part
of the macro library file (like IBIS_IO)?
Also, in this example, the Verilog-A file is directly run in hspice. My idea of
the
final product would be, the IBIS file is instanced in hspice using the b-elem
and that
ibis file's model would (only?) have an [external circuit] reference to the
verilog-A
file. Is this correct?
---------------------
As far as the proposed IBIS to Verilog-A converter goes:
1. What is the purpose here?
2. Taking the 2-tap preemphasis buffer as an example, could you explain what it
means to
convert its IBIS file to a Verilog-A instance, given that the only initial file
available is its hspice netlist?
Regards,
Paul Fernando
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