Walter
Your first email. I have to disagree, there is no requirement to have a GND
or 0.00V pin on an IC. As an aside, there is also no requirement to have a
POWER pin on an IC, I'm in the process of modeling a part that has several
digital inputs, some analog pins and several GND pins but no power pin.
Your second question. As the frequency of a signal increases the distance
between the signal you are measuring and its reference node need to be
closer and closer. Any distance between the two test points forms an
inductive loop. That inductance is in series with the measurement. There
is a similar criteria for input capacitance. As the signal frequency goes
up the input shunt C of the measurement system must decrease. And likewise
with resistance for all frequencies, the resistive component of the probe
must not load the circuit. This RLC circuit of the effective probe must not
limit the bandwidth of the signal delivered to the resistive part of the
probe nor load the circuit. BTW, if R is infinite and C is 0.000pF then the
value of the inductance is immaterial. But with real world systems it is
important to minimize the L in the measurement probing system.
On the other hand you don't want the contributions of stray currents flowing
around the board contributing to the measured signal. You can minimize this
by keeping the signal and return probe points as close as possible.
But close has to include the fact that there has to be a continuous return
path between the point you are using as the return path (gnd) and the
signal.
But I'm not sure what you are trying to get at here. You can measure the
voltage of any pin relative to any local GND or Power. There is no need for
that reference voltage to be in the chip.
Regards,
Tom Dagostino
971-279-5325
tom@xxxxxxxxxxxxxxxxx
Teraspeed Labs
9999 SW Wilshire Street
Suite 102
Portland, OR 97225
-----Original Message-----
From: Walter Katz [mailto:wkatz@xxxxxxxxxx] ;
Sent: Tuesday, July 12, 2016 11:58 AM
To: Tom Dagostino; bob@xxxxxxxxxxxxxxxxx; IBIS-ATM
Subject: RE: [ibis-macro] Re: Pin Reference Concerns
Tom,
To be clear, a voltage measurement is between two points that must be close
together. Close is a nebulous term, but should be << 1UI, and certainly <~
the maximum frequency of interest of the measurement being made. At 3Gbps,
the maximum frequency one should be concerned with should be at least 15GHz.
This is 30ps or <.2". So making any voltage measurement at the rail of a
buffer must be made within .2" of the buffer. This is a point within the
chip, certainly within the package. So the reference for any voltage
measurement must be inside the package and therefore supplied by a package
pin.
This is basic to any electrical measurement, do you agree, and if not, why
not?
Walter
-----Original Message-----
From: Walter Katz [mailto:wkatz@xxxxxxxxxx]
Sent: Tuesday, July 12, 2016 2:32 PM
To: Tom Dagostino <tom@xxxxxxxxxxxxxxxxx>; bob@xxxxxxxxxxxxxxxxx; IBIS-ATM
<ibis-macro@xxxxxxxxxxxxx>
Subject: RE: [ibis-macro] Re: Pin Reference Concerns
Tom,
You are correct, but there must be a Pin on the component (e.g. VSS or
GND) that is 0.0V in the data book. This must be the reference node for the
voltage measurement on the pins of the model. True, this 0.0V pin is not one
of the rail voltages connected to the buffer model, but this 0.0V pin must
exist, otherwise how can you measure the rail voltages at the buffer.
Walter
-----Original Message-----
From: Tom Dagostino [mailto:tom@xxxxxxxxxxxxxxxxx]
Sent: Tuesday, July 12, 2016 2:26 PM
To: wkatz@xxxxxxxxxx; bob@xxxxxxxxxxxxxxxxx; 'IBIS-ATM'
<ibis-macro@xxxxxxxxxxxxx>
Subject: RE: [ibis-macro] Re: Pin Reference Concerns
Walter
I sent you a model back in March of an ECL part that operated between Vcc =
2.0V and Vee = -0.5V. Could you please point out in that model the GND or
0.000V pin?
Because attachments are not allowed I'll copy relevant parts of the model
here.
[Pin] signal_name model_name R_pin L_pin C_pin
|
1 VCC POWER 1.000E-02 1.720E-09 4.240E-13
2 IN+ in 1.000E-02 1.720E-09 4.240E-13
3 IN- in 1.000E-02 1.720E-09 4.240E-13
4 CLK4+ clk4 1.000E-02 1.720E-09 4.240E-13
5 CLK4- clk4 1.000E-02 1.720E-09 4.240E-13
6 VEE POWER 1.000E-02 1.720E-09 4.240E-13
|
|****************************************************************
[Model] in
Model_type Input
Vinl = 350.000mV
Vinh = 550.000mV
C_comp 785.000fF 778.000fF 792.000fF
|
| variable typ min max
[Voltage Range] 2.00000V 2.000V 2.00000V
[POWER Clamp Reference] 2.00000V 2.000V 2.00000V
[GND Clamp Reference] -0.50000V -0.500V -0.50000V
[Temperature Range] 25 85 -40
[Model] clk4
Model_type Output_ECL
Vref=0.000E-01
Rref=5.000E+01
Cref=0.000E+00
Vmeas=0.450E+00
C_comp 1.430E-12 1.370E-12 1.450E-12
|
|
[Voltage Range] 2.000E+00 2.000E+00 2.000E+00
[POWER Clamp Reference] 2.000E+00 2.000E+00 2.000E+00
[GND Clamp Reference] -0.500E+00 -0.500E+00 -0.500E+00
[Pullup Reference] 2.000E+00 2.000E+00 2.000E+00
[Pulldown Reference] 2.000E+00 2.000E+00 2.000E+00
Are there designs that use split power delivery to ECL parts? Yes, I have
some test cards from a couple of ECL vendors that use the split rails for
their test. It allows the signal generator and scope they use in test to
remain at a 0.00V level, properly terminating the output and make the
correct DC measurements - no AC coupling required.
The Vref in the model is 0.00V. It is expressed this way because IBIS does
not allow equations for voltages. Vref is really Vcc - 2 V. To get around
this limitation [Model Spec] was invented so the Vref can show the proper
voltages for the three different corner cases. Likewise for Vinl and Vinh.
These voltages are really referenced to Vcc for an ECL input.
Describing where the current flows in a circuit tells you which power rails
will influence the input and output levels of the device. For the ECL
example, all the output currents flow in the Vcc rail, none flows in the Vee
rail. That tells you the output levels will track the Vcc supply.
Varying the Vee rail will not influence the output Hi or Low voltage.
Varying Vcc will change the output voltages.
For a CMOS device the current flows in Vdd when the part is high so the
output high is directly related to Vdd. Likewise current flows through the
Vss pin when the driver is low and any change in Vss will change the low
voltage. In a typical reflected wave switching CMOS net output high is not
a function of Vss but is directly affected by Vdd and output low is not a
function of Vdd but directly affected by Vss.
Regards,
Tom Dagostino
971-279-5325
tom@xxxxxxxxxxxxxxxxx
Teraspeed Labs
9999 SW Wilshire Street
Suite 102
Portland, OR 97225
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Tuesday, July 12, 2016 9:43 AM
To: bob@xxxxxxxxxxxxxxxxx; IBIS-ATM
Subject: [ibis-macro] Re: Pin Reference Concerns
Bob,
Your whole discussion about ECL is a total obfuscation. Current flow is no
consideration on how to measure voltages at a buffer relative to a reference
node in the component. On slide 12 your statement " A VSS pin (GND DUT
connection) does not always exist" is totally incorrect. If there is not
such pin (GND DUT connection) how does the test fixture measure the voltages
at the I/O rail terminals? We MUST INSIST that all measurement be made close
to the buffer, at least inside of the component. This is a basic requirement
of any measurement of a buffer voltage.
Walter
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Bob Ross
Sent: Tuesday, July 12, 2016 12:33 PM
To: 'IBIS-ATM' <ibis-macro@xxxxxxxxxxxxx>
Subject: [ibis-macro] Pin Reference Concerns
All,
As a head's up, here is the presentation I plan to discuss at today's
meeting (July 12, 2016).
Bob
--
Bob Ross
Teraspeed Labs
http://www.teraspeedlabs.com
bob@xxxxxxxxxxxxxxxxx
Direct: 503-246-8048
Office: 971-279-5325
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