[ibis-macro] Minutes from the 19 dec 2006 ibis-atm meeting

  • From: "Doug White \(dowhite\)" <dowhite@xxxxxxxxx>
  • To: <ibis-macro@xxxxxxxxxxxxx>
  • Date: Fri, 5 Jan 2007 09:38:19 -0500

Minutes from 12/19 meeting attached.
 
        
Doug White
Technical Leader
RSPTG Design Services and Operations

dowhite@xxxxxxxxx
Phone :919.392.4103
Fax :919.392.3902



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IBIS Macromodel Task Group

Meeting date: 19 Dec 2006

Members (asterisk for those attending):
* Arpad Muranyi, Intel Corp.
* Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
* Doug White, Cisco Systems
* Hemant Shah, Cadence Design Systems
* Ian Dodd, Mentor Graphics
  Joe Abler, IBM
  John Angulo
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
* Kumar, Cadence Design Systems
* Lance Wang, Cadence Design Systems
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
  Randy Wolff, Micron Technology
  Richard Ward, Texas Instruments
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence
* Todd Westerhoff, SiSoft
* Walter Katz, SiSoft
  Vuk Borich, Agilent
  Vikas Gupta, Xilinx

-------------
Review of ARs:

- Mike update macro library documentation
  Will send I/O doc to Arpad for review soon.

- Kumar: Incorporate some of the terminology, as presented in the
  SiSoft presentation, into the API proposal, especially into
  the examples.
  - done

- HSpice Syntax
  No reply yet, inquiries sent to Synopsys.

- Parameter Passing BIRD
  No update


-------------
New Discussion:

AR:  Mike will add Kumar and Hemant to the email list.

Everyone agrees with linear/time-invariant assumption for the API proposal.
If system is not LTI, how do we estimate how far off the results will be?
Ian may have an algorithm to determine if a model is LTI.
GTL buffer may be too non-linear for this approach.
Another assumption that seems to be implicit in our API discussions so far is 
the "superposition" principle applied to the pulse response.
Pulse response can be used to create a step response - will this match an 
original step response?
Walter:  Need to define "risetime" and "falltime"...is it differential or 
singled-ended?
If differential rise edge is different from fall edge, this may cause problems 
for analysis (phase noise amplification?)
We might want to limit to 7GB serdes, LTI, to allow tools to analyze any way 
they want.
LTI will not work at lower frequencies, with typically nonlinear I/O.

Walter: Models should be supplied with a test deck and golden waveforms.  There 
should be some standard format for exchanging
        information, so software can be validated, regression tests can be 
done, etc.
IBIS Golden waveforms are use for silicon lab measurements, may not work for 
channel analysis.

S-params give characteristics of "ideal" impulse response, but only as far as 
the frequency range allows.

New Cadence presentation using Todd's terminology
  Still some questions about what the arrows in the flow diagrams mean and 
their directions
  "Impulse Response", as the term is used in the prez, is for TX front-end, 
channel, and RX front-end
  Todd:  But there is a difference between (1) "extraction" of an impulse 
response, where the frequency-domain
         response would be obtained by circuit or field-solved extraction 
method, then the impulse response obtained by IFFT, and (2) "simulated" impulse 
response,
         where the impulse response would be obtained using a circuit 
simulation of the real I/O models and channel, perhaps a very fast step, and 
then from there
         transformed to an impulse response.  So which are we talking about???
  This impulse response, passed at INIT, does it include the TX filter?
  Kumar:  It can, yes.
  Kumar: Impulse response can be approximated using the real I/O models and 
channel using a circuit simulation.
  Arpad: What about a frequency domain approach for the simulation?

TX should not optimize itself, EDA tool should do it
SiSoft proposes that API not needed to model TX
Kumar:  Optimization will be algorithm dependent.

***Question for semiconductor vendors:  Is it feasible to come up with a 
well-defined standard model (type) for the TX, and let the EDA tools do the 
optimization?***


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Next meeting: Tuesday 09 Jan 2006 12:00pm PT

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  • » [ibis-macro] Minutes from the 19 dec 2006 ibis-atm meeting