[ibis-macro] Minutes from the 12 Nov 2013 ibis-atm meeting

  • From: Mike LaBonte <mike@xxxxxxxxxxx>
  • To: ibis-macro@xxxxxxxxxxxxx
  • Date: Mon, 18 Nov 2013 10:30:42 -0500

Minutes from the 12 Nov 2013 ibis-atm meeting are attached.

IBIS Macromodel Task Group

Meeting date: 12 November 2013

Members (asterisk for those attending):
Agilent:                      Fangyi Rao
                              Radek Biernacki
Altera:                       David Banas
                              Julia Liu
                              Hazlina Ramly
Andrew Joy Consulting:        Andy Joy
ANSYS:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
                              Steve Pytel
                              Luis Armenta
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
                              Feras Al-Hawari
                            * Brad Brim
                              Kumar Keshavan
                              Ken Willis
Cavium Networks:              Johann Nittmann
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                        Michael Mirmak
Maxim Integrated Products:    Mahbubul Bari
                              Hassan Rafat
                              Ron Olisar
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
                              Vladimir Dmitriev-Zdorov
Micron Technology:          * Randy Wolff
                            * Justin Butterfield
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:       Eckhard Lenski
QLogic Corp.                  James Zhou
SiSoft:                     * Walter Katz
                            * Todd Westerhoff
                              Doug Burns
                            * Mike LaBonte
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla
                              Ray Anderson

The meeting was led by Arpad Muranyi


- Arpad asked if any upcoming meetings would have to be canceled.
- Arpad will miss the next two meetings
  - Mike will chair
  - John will host web sharing
  - Curtis will take minutes

Call for patent disclosure:

- None

Review of ARs:

- None

New Discussion:

Arpad asked if we should discuss the backchannel topic.
- No one asked to open that discussion.

IBIS Component vs. EBD/EMD:
- Walter showed an email showing proposed new keywords.
- Walter: A list of supply die pads is needed to join silicon and package 
supply routing.
  - A [Buffer Supplies] keyword is also needed.
- Arpad: Why is the second column needed?
- Walter: It is needed to identify the pads that are connected with low 
  - The implication is that they are connected somewhere.
- Walter: Each buffer would list its power, ground, pclamp, and gclamp supplies.
  - The first column of [Buffer Supplies] is the component pin name.
- Ambrish: Is there a way to do this with [External Circuit]?
- Walter: You also need to identify the die supply pads.
  - Brad had asked if those were really needed.
  - If the silicon and package power distribution are extracted separately, in 
some cases
    die pads will be involved.
  - It is possible that it can be done without die pads, going from pin to 
  - We should support both approaches.

- Arpad: We might also have RDL present.
- Walter: RDL should be part of the silicon, but traditionally is part of the 
- Arpad: Someone may want to have it separate.
- Brad: We are only required to provide one M to N connection block.
  - Supporting more cascaded sections adds convenience.
- Walter: I believe RDL is always included in some other model.

- Walter described [Stacked Memory] and [Pin Stacking].
- Bob: Where do the subckts come in?
- Walter: Something like MCP would give the mapping.
- John: Are there any restrictions on the IBIS models used with this?
- Walter: It is assumed they are all identical, A1 is the same buffer on each.
- John: It seems the difference between this and EBD/EMD is small.
- Walter: Yes this could be done with EBD/EMD.
- John and Walter agreed that complications could arise.
- John: We would need EBD/EMD if we needed to break the 1 pin to 1 buffer 
- Arpad: What do model makers want?
- Randy: We would like a stacked memory mechanism.
  - It would allow some pieces to be in the same file.
  - How to include on-die interconnect must be described in the IBIS file.

IBIS Interconnect SPICE Wish List:

1) Simulator directives

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