[ibis-macro] Minutes from Sep 2008 ibis-atm meetings are attached
- From: "Mike LaBonte (milabont)" <milabont@xxxxxxxxx>
- To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 7 Oct 2008 14:14:21 -0400
Minutes from Sep 16, 23, and 30 ibis-atm meetings are attached. These
are also posted online in the Meeting Minutes area at
http://www.eda.org/pub/ibis/macromodel_wip/
Mike
IBIS Macromodel Task Group
Meeting date: 23 September 2008
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
* Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
Essaid Bensoudane, ST Microelectronics
Fangyi Rao, Agilent
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
Ian Dodd, Agilent
Joe Abler, IBM
* John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
Sam Chitwood, Sigrity
Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
-----
Opens:
--------------------------
Call for patent disclosure:
- No one declared a patent.
-------------
Review of ARs:
- David Banas report Xilinx position on LTI assumption for SerDes
- LTI is a good enough assumption for SerDes models
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
Michael M Presentation: Proposal for New Keywords to Improve Buffer Impedance
Modeling
- Page 4:
- This allows for parallel RC circuits in addition to C_comp
- Improves both time and freq domain modeling.
- Supports JEDEC DDR Rdie approach
- JEDEC Rdie is not the same as Rdie as used in power delivery tools
- Square box at right side is the pad.
- Page 6:
- Voltage dependence may cause problems for the LTI assumption.
- David: C_comp will be state dependent.
- Mike L: Is C_comp different in high and low states?
- Yes, Arpad published a study on this in his training class.
- David: Looking at actual data, the H/L difference is smaller than on/off
- There is no statement here about typ/min/max corner relationships for
C_Comp.
- Bob: Is there a defined method to extract this?
- Michael M: There are some crude methods
- Page 8:
- Methods to calculate C_comp:
- 1: C = I/dVdt
- Time domain simulation is used for this
- David: Xilinx gets good results with this method
- 2: Hazem Hegazy described an LC tuned circuit method
- 3: AC analysis
- This is described in the IBIS cookbook
- Page 10:
- Michael M: We need to allocate C_comp correctly
- It must be correct in both input and output mode
- Page 11:
- Proposed fix: adjust V-T tables for total C_comp
- Page 13:
- C_comp is very Freq dependent, V dependent to a lesser degree
- Page 14:
- Luca Giacotto and Arpad Muranyi created a model for this
- Buffer impedance can be modeled with an RC ladder
- Pages 15 & 16:
- Ladder RC correlation to transistor SPICE much better than single C
- Page 19:
- Proposal: Create a fixed circuit template with 3 Rs and 3 Cs
- Good up to 2GHz
- Michael M: We should have a better impedance representation:
- It must be better than I-V tables
- It must be better than single C_comp
- How do we resolve the charge storage problem?
- How do we resolve state dependence?
Walter: An external interconnect subckt could be used for this
- We would have to allow table driven resistors and capacitors
- Some companies are using S-param models for TX/RX
- The subckt should have ports for driver enable/stimulus
- This would allow modeling of state dependence
- Todd: We could use an arbitrary subckt instead of creating a fixed structure
- Michael M: It may be tricky to make buffer simulation work with arbitrary
circuits
- Arpad: This is a can of worms: an external subckt might have a transistor
model
- Todd: It depends on what elements we allow
- Walter's proposal would still have V-T tables.
- Waveforms should be stored unprocessed.
- Michael M: Assume traditional SPICE not used to characterize IBIS data
- Arpad: Clarification: the proposed subckt is in addition to I-V tables
- Michael M: It is important to note that V-T curves have to de-embed C_comp
structure
- Otherwise C_comp will be double counted
- Arpad: One solution is to directly model K factor curves
- This would bypass the "IBIS kernel" that calculate K factor
- Bob: C_comp structures can be de-embed from waveforms at simulation time
- Gets around the [Driver Schedule] problem
- Todd: Would this process assume the subckt contents are a black box?
- Michael M: We should try to salvage traditional IBIS extraction methods
- Arpad: If we model K factor directly, we could have done this in the AMS model
- The model maker will have more work in this case
- Todd: The 7 terminal IBIS buffer is nothing more than an IBIS SPICE element
- Arpad: Then we only need to add RC branches
- Walter: We would want to have S-param elements too
- Walter: We must clarify that these are not interconnect circuits
We will continue next week
Next meeting: 07 October 2008 12:00pm PT
-----------
IBIS Macromodel Task Group
Meeting date: 16 September 2008
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
Essaid Bensoudane, ST Microelectronics
Fangyi Rao, Agilent
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
Ian Dodd, Agilent
Joe Abler, IBM
* John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
* Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
Sam Chitwood, Sigrity
Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
Terry Jernberg, Cadence Design Systems
Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
-----
Opens:
- Review Walter's document.
--------------------------
Call for patent disclosure:
- No one declared a patent.
-------------
Review of ARs:
- David Banas report Xilinx position on LTI assumption for SerDes
- No update
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
1. Finalize the IBIS-SPICE document draft to be sent to Synopsys.
- Michael: Synopsys is not available for discussion for a couple of weeks.
- Would like them to join this meeting or discuss offline.
- Showed the document IBIS-Interconnect-Spice-mm.doc.
- He added a preamble to explain the scope of the proposal.
- Arpad: We might want to support encryption such as will be defined by
the P1735 standard.
- Michael: The document intentionally does not list a vendor specific SPICE
in the assumptions section.
- "Frequency-domain network parameters" was added to the scope section.
- Radek: The scope should not limit the intended use of the models.
- Arpad: Don Telian when working for Cadence wanted to donate K-SPICE.
- Should we approach Cadence about a donation of K-SPICE again?
- K-SPICE may have too many non-standard features in the controlled sources.
- Walter: We should approach Synopsys first before contacting Cadence.
- Michael: In the S-element section, should we include the Zo value?
- Walter: Thought the value was already in the Touchstone file.
- Michael: The parameter could be a check or to force a conversion from
one impedance to another.
- Radek: The value should come from the Touchstone file.
- Michael: We'll have to study that more. Also, only S and Y are mentioned.
- Michael: No B-element is included.
- Walter: There is a shunt element which is an independent source, but
it is the only one. We don't want any other independent elements.
- Arpad: What is the next step?
- Michael: He will clean up the document and discuss next week.
2. Walter showed changes to last week's presentation "Block Diagram View of
EMD."
- Bob: On page 1, what are the black arrows representing?
- Walter: These are direct connections between blocks.
- Bob: Can an EMD file be a module consisting of modules?
- Walter: Yes, it can be used to wrap up an entire system.
EMDs can be nested.
- Arpad: Can we post this document now?
- Walter: He will send it to Mike LaBonte.
3. Agenda for next week:
Will review Michael's document changes.
Next meeting: 23 September 2008 12:00pm PT
-----------
IBIS Macromodel Task Group
Meeting date: 23 September 2008
Members (asterisk for those attending):
Ambrish Varma, Cadence Design Systems
Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
Barry Katz, SiSoft
Bob Ross, Teraspeed Consulting Group
Brad Brim, Sigrity
Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
Donald Telian, consultant
Doug White, Cisco Systems
Essaid Bensoudane, ST Microelectronics
Fangyi Rao, Agilent
Ganesh Narayanaswamy, ST Micro
Gang Kang, Sigrity
Hemant Shah, Cadence Design Systems
Ian Dodd, Agilent
Joe Abler, IBM
* John Angulo, Mentor Graphics
John Shields, Mentor Graphics
Ken Willis, Cadence Design Systems
Kumar
Lance Wang, Cadence Design Systems
Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
Mike Steinberger, SiSoft
* Mustansir Fanaswalla, Xilinx
Patrick O'Halloran, Tiburon Design Automation
Paul Fernando, NCSU
* Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
Ray Comeau, Cadence Design Systems
Richard Mellitz, Intel
Richard Ward, Texas Instruments
Sam Chitwood, Sigrity
Sanjeev Gupta, Agilent
Shangli Wu, Cadence Design Systems
Sid Singh, Extreme Networks
Stephen Scearce, Cisco Systems
Steve Pytel, Ansoft
Syed Huq, Cisco Systems
Syed Sadeghi, ST Micro
Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
Vikas Gupta, Xilinx
Vuk Borich, Agilent
* Walter Katz, SiSoft
Zhen Mu, Cadence Design Systems
-----
Opens:
- Review Walter's document.
--------------------------
Call for patent disclosure:
- No one declared a patent.
-------------
Review of ARs:
- Michael M: Clean up the document for discussion in next meeting
- Done
- Walter: Send modified EMD slides to Mike LaBonte for posting
- Sent Sep 16 and posted
- David Banas report Xilinx position on LTI assumption for SerDes
- LTI is a good enough assumption for SerDes models
- Arpad: Write parameter passing syntax proposal (BIRD draft)
for *-AMS models in IBIS that is consistent with the
parameter passing syntax of the AMI models
- TBD
- TBD: Propose a parameter passing syntax for the SPICE
- [External ...] also?
- TBD
- Arpad: Review the documentation (annotation) in the macro libraries.
- Deferred until a demand arises or we have nothing else to do
-------------
New Discussion:
Review of revised document for presentation to Synopsys
- This is written to be generic, it could go to any vendor.
- It will not include encryption support except for P1375
- David: Have model makers requested encryption of interconnect models?
- No
- Correction: Some single quotes were changed to backquotes by the editor tool.
- We should document scaling prefixes, one of:
- MEG for mega, M for milli
- M for mega, m for milli
- X for mega
- Correction: Node numbers extend from 1 to 1e16-1, not 1e16
- In Berkeley SPICE node names that begin with a digit ignore subsequent letters
- We added the Inductor element
- Is Foster Pole-Residue common, or is Foster a variant ?
- Radek: Foster is the creator of the format
- The W element will only support .MODEL syntax
- We need to drop the RLGCFILE parameter
- .INCLUDE can instead be used for external .MODELs
- Radek: Raw RLGC files are useful for static models.
- Randy: Many tools use this format
- Michael M: We could leave it but not document the format.
- Radek: Table model format specifies frequency for each matrix
- Michael M: The W element NODEMAP is critical for certain applications
- Randy: The encryption standard mentioned previously is actually P1735
- Michael M: P1735 is a public standard for a macro language to express
encryption
- Arpad: Should we allow expressions to be used other than as constants?
- Michael M: Too much detail:
- Right now we are trying only to get past the permission problem
- Once we have permission, vendors can add proprietary content
- Arpad: In the node name discussion is (:) correct for concatenation?
- It probably should be (.)
- Michael M: This should be enough to begin the discussion with Synopsys
- They can meet next week
- Arpad: Will we bring Synopsys into our meetings?
- Michael M: We will work with them offline
Should we talk about die capacitance characterization next week?
- It is not yet an official BIRD
Arpad: We had hoped at one time to avoid creating more keywords
- Michael M: Having a methodology to guide us would help
- Walter: It might be done with an extension of interconnect SPICE
Walter: The updated EMD document has been posted and is ready for review.
Next meeting: 30 September 2008 12:00pm PT
-----------
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