[ibis-macro] Minutes from 16 aug 2005 ibis-macro phone call

  • From: "Mike LaBonte (milabont)" <milabont@xxxxxxxxx>
  • To: <ibis-macro@xxxxxxxxxxxxx>
  • Date: Tue, 16 Aug 2005 16:28:58 -0400

Minutes from the 16 aug 2005 ibis-macro phone call are attached.
meeting date: 16 aug 2005
attending: Arpad Muranyi, Mike LaBonte, Todd Westerhoff, Ian Dodd, Bob Ross
           Barry Katz

AR Review:
AR: Arpad will send letter to Geoffrey Ying @ synopsys
- Sent, no response yet.
AR: Arpad will send reflector info
- Talked to Michael Mirmak. No public minutes. Could be downloaded though.
AR: All read verilog-AMS LRM:
- oops.
AR: Arpad will convert his pre-emphasis buffer example to use building blocks
    based on Mike's skeleton library
- Some progress.

Discussion of Verilog-AMS LRM "SPICE compatibility" section:
- Sounds like BIRD75.
- Sounds similar to what we are doing.

Recap where we are:
- Started with free-form discussions on how to carry Donald Telian Macromodel
  campaign forward.
- How to put it in IBIS itself? Not as beneficial as using an IBIS-approved
  language and building macromodels within it.
- Standard building blocks in AMS will do the job.
- Everyone can wire building blocks together. Standard library elements
  can be rewritten in any language.
- Hope is to have identical libraries in Verilog and VHDL.

Arpad's latest capacitor model:
- Adds to Mike's starter library.
- Arpad added charge conservation.
  - Charge variable needs to be initialized.
  - What if capacitance changes on the fly?
  - Is the capacitance param static anyway?
- Mentor recommends users set initial conditions.
  - Arpad's model does this with V0.
- Questions about complexity of charge conserving model
  - We will create 2 cap models, conserving and non-conserving.

AR: Arpad continue work on library

What to show at DesignCon:
- pre-emphasis buffer:
  - Arpad looked at Ken's macromodel.
  - What are we trying to do with that file? Do we need to do everything
    it does?
  - We showed a working pre-emphasis example at summit.
    - Cadence macro matches what Arpad has already shown.
    - What else does Cadence have?
- simple IBIS buffer?
- How about a nGHz receiver model?
  - can it be done using building blocks?
  - should it be a new building block?
  - Mentor has a receiver building block
    - Not sure if it can be made public.

AR: Ian find out if Mentor receiver can be public

String literals:
- B element has hard-coded file name
- Can't have a library element for each IBIS file
- How to pass in string variables?
- Talk of 2.3 LRM
  - Consumed by talk of System Verilog (C++ interfacing) as 3.0 release
  - Some pressure to make params usable
- String param can be passed, but not used for file name
- Can have macro that expands to file name.
- No good solution
- Could have a naming convention that puts IBIS file and model name into
  the macro name.
  - non-Verilog simulators would have to synthesize equivalents on the fly
- VHDL does not have this problem
- HSPICE can have string as param beginning with ???
- Library needs 2 sections:
  - static building blocks
  - ones that need processing

IBIS summit:
- We will present a report
- Just a question of how much we have ready.
- Arpad not sure about traveling to DesignCon East.
  - May be worth it if we present something big.

AR: All read "SPICE Compatibility" section of:

Next meeting: Tuesday August 23, 2005.

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