[ibis-macro] Latest macro library release for Verilog-A(MS) and VHDL-A(MS)
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Thu, 26 Jan 2006 23:14:23 -0800
Hello everyone,
The long awaited first release of the VHDL-A(MS) macro model
library has been posted to the IBIS macro modeling website
along with an updated version of the Verilog-A(MS) version.
You can access them at:
http://www.eda.org/pub/ibis/macromodel_wip/Macro_Lib_VA_HSPICE_2006_01_26.zip
http://www.eda.org/pub/ibis/macromodel_wip/Macro_Lib_VHDL_SMASH_2006_01_26.zip
Comments:
1) These libraries do not include Mike's comments yet.
Mike, would you be so kind and add them in with your program?
2) The Verilog-A(MS) has a lot of mostly cosmetic changes, the
technical content is pretty much the same as before.
This was done to make is as similar to the VHDL-A(MS) version as
possible so that people can read them kind of side by side as far
as possible. So I made sure that the variable names are spelled
the same way wherever possible, etc...
3) The examples which use array parameters in the Verilog-A(MS)
library (PWL and IBIS buffer building blocks) currently will only
work in HSPICE if the length of the array parameter passed into
the module is the same as the array length inside the module due
to a bug in the compiler. I heard from the compiler vendor that
this bug is being fixed and a new version will be available soon.
4) There is an independent test case for each library element in
both language implementations. Again, the goal was to match the
test cases of the two languages as far as possible, so that the
results could also be compared easily.
5) The format of the test cases are the same in both languages.
There is a top level stimulus circuit in the SPICE language. Then
there is a VHDL-A(MS) or Verilog-A(MS) netlist which instantiates
one building block from the library. This netlist is the equivalent
of the "Macro Model Template" in our terminology.
6) In the HSPICE examples the SPICE and VA sections are in two
different files, the .SP and the .VA files. In the SMASH examples
the SPICE and VA sections are in one file, the .NSX files, and the
simulation control statements are in another file, with the .PAT
extension. For both cases the library is in a subdirectory called
"Macro_lib". This subdirectory also has some data files which contain
the IBIS parameters (IV and Vt curves, C_comp, etc...) for the IBIS
building blocks in the library.
7) I am still not too happy with the parameter passing in the
VHDL-A(MS) netlists, and I am hoping to hide away those longs list
of parameters there. This is work in progress, but this should not
have any effect on how the library itself works.
8) The VHDL-A(MS) library was developed with a tool called SMASH by
Dolphin.
http://www.dolphin-integration.com/medal/smash/smash_overview.html
This tool has a free evaluation version called SMASH Seduction:
http://www.dolphin.fr/medal/smash/smash_download.html
Due to the limitation of this evaluation version (30 quantities) I had
to comment out a few (minor) things in the library to make it work.
This is the receiver logic in the I/O buffer types. Everything that
is needed is in the code, except you will see some of the lines
commented out.
9) SMASH has an interesting artifact when it compiles the library.
It will compile the library into a subdirectory named after the .NSX
file. This means that the same library having 63 test cases will be
compiled 63 times if you let SMASH do it. This is quite time consuming,
so I decided to store a compiled version of the library under the
"Macro_lib" directory along with a DOS batch file which will copy it 63
times for each test case. Executing this batch file is much faster than
letting SMASH compile the entire library 63 times, so I would recommend
that before doing anything else, execute the "Copy_lib.bat" file under
the "Macro_Lib" directory first. It will same you a lot of time...
After that all you need to do is to double click on any of the .NSX
files which will start SMASH. Once it is up, you can just press
Ctrl-T to run a transient simulation of the file that is open. The
waveform viewer will open automatically when it is done. Note, this
step is only applicable to the VHDL-A(MS) library test suite.
I hope I didn't forget anything. Please look it over and try it out
if you can. Any questions and comments are welcome.
Thanks,
Arpad
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