All,
For the new package modeling, No. The assumption is that the person
writing the package model knows what the reference pin is for each model.
How does he know, he reads the data book for the component.
Who would use this [Pin Reference] info?
1. The Package and PCB designer might use this to make sure that the
I/O connection is "imaged" (aka valid return path) correctly.
2. The EDA tool might use this to correctly reference the package
models where "Node 0" is currently implied
a. For RLC, and [Define Package Model] path records, package
capacitors and wlines for each connection would be "referenced" to the
signal name defined by the [Pin Reference]
i.
Default would be to a *_ref terminal that had [*_Reference]=0.
b. [Define Package Model] matrix records have only one reference, so
this would only work if the [Pin Reference] was the same on all of the
pins in the matrix.
Walter
Walter Katz
<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx
Phone 303.449-2308
Mobile 303.335-6156
