All,
I fixed my slides and checked with Walter off line, and he agreed that the
correction
I made is god now. In addition to that, I revised the slides so that the text
from Walter's
email is now also included, side by side with my drawings. This should make it
a lot
easier to read. I hope I didn't make any mistakes in doing so.
I also added an introductory slide to the slides for my examples to make clear
what the
assumptions are for those.
The attached PDF file is now what I would consider "worthy" for being posted in
our
archives. Please feel free to make questions/comments.
Thanks,
Arpad
=====================================================================
From: Muranyi, Arpad
Sent: Wednesday, March 21, 2018 2:07 AM
To: IBIS-Interconnect <ibis-interconn@xxxxxxxxxxxxx>
Subject: RE: Is A_gnd Model or Component
Walter,
In trying to understand your examples better, I made a drawing for each of them.
Could you please make sure that I got it right? I would like to discuss this
in the
Interconnect meeting, along with the slides I made for my AR.
Thanks,
Arpad
================================================================
From:
ibis-interconn-bounce@xxxxxxxxxxxxx<mailto:ibis-interconn-bounce@xxxxxxxxxxxxx>
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Tuesday, March 20, 2018 3:03 PM
To: IBIS-Interconnect
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>
Subject: [ibis-interconn] Re: Is A_gnd Model or Component
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
978.461-0449 x 133
Mobile 303.335-6156
From: Walter Katz <wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>>
Sent: Friday, March 16, 2018 1:31 PM
To: 'IBIS-Interconnect'
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>
Subject: Is A_gnd Model or Component
All,
I am going to use as my example a 6 pin component, an extension of the example
I sent out earlier today.
Interconnect model sets Set3 and Set4 use A_gnd. In the models in Set3, each
interconnect model has a unique I/O pin_name. So I can hook the third terminal
in model DQ in Set3 to either
1 Pulldown_ref pin_name 1 A_gnd is local to that buffer
2 Buffer_Rail signal_name VSSQ A_gnd is local to the die
3 Pin_Rail signal_name VSSQ A_gnd is local to the component
4 Node 0 A_gnd is the
global "Node 0"
In the models in Set4, I am stuck since DQ and CMD have different reference
signal names, and I would be forced to use Node 0.
[Pins]
1 DQ IO
2 CMD In
3 VSS GND
4 VSSQ GND
5 VDD POWER
6 VDDQ POWER
|
[Model] DQ
Model_type I/O
[Model] In
Model_type Input
|
[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref
power_clamp_ref ext_ref
1 VSSQ VDDQ NC NC
NC
2 NC NC VSS VDD
NC
|
[Interconnect Model Group] Group1
Set1 NA
Power NA
[End Interconnect Model Group]
[Interconnect Model Group] Group2
Set2 NA
Power NA
[End Interconnect Model Group]
[Interconnect Model Group] Group3
Set3 NA
Power NA
[End Interconnect Model Group]
[Interconnect Model Group] Group4
Set4 NA
Power NA
[End Interconnect Model Group]
[Interconnect Model Set] Power
[Interconnect Model] my_power
File_IBIS-ISS my_power.iss my_power
Number_of_terminals=8
1 Pin_Rail signal_name VDD
2 Pin_Rail signal_name VDDQ
3 Pin_Rail signal_name VSS
4 Pin_Rail signal_name VSSQ
5 Buffer_Rail signal_name VDD
6 Buffer_Rail signal_name VDDQ
7 Buffer_Rail signal_name VSS
8 Buffer_Rail signal_name VSSQ
|.subckt my_power Pin_VDD Pin_VDDQ Pin_VSS Pin_VSSQ Buf_VDD Buf_VDDQ Buf_VSS
Buf_VSSQ
| R1 Pin_VDD Buf_VDD .1
| R2 Pin_VDDQ Buf_VDDQ .1
| R3 Pin_VSS Buf_VSS .1
| R4 Pin_VSSQ Buf_VSSQ .1
|.ends my_power
[End Interconnect Model
|.subckt my_power Pin_VDD Pin_VDDQ Pin_VSS Pin_VSSQ Buf_VDD Buf_VDDQ Buf_VSS
Buf_VSSQ
| W1 Pin_VDD 0 Buf_VDD 0 .1 L=... RLGC=...
| W2 Pin_VDDQ 0 Buf_VDDQ 0 .1
| W3 Pin_VSS 0 Buf_VSS 0 .1
| W4 Pin_VSSQ 0 Buf_VSSQ 0 .1
|.ends my_power
| Ground Based Power Aware Models
| Assumes that VSS and VSSQ are connected to Node 0 with 0 Ohm
resistor:
| V1 VSS 0 DC=0.
| R1 VSS 0 .000001
|.subckt my_power Pin_VDD Pin_VDDQ Pin_VSS Pin_VSSQ Buf_VDD Buf_VDDQ Buf_VSS
Buf_VSSQ
| W1 Pin_VDD 0 Buf_VDD 0 .2
| W2 Pin_VDDQ 0 Buf_VDDQ 0 .2
|.ends my_power
[Interconnect Model Set] Set1
[Interconnect Model] all_signal
File_IBIS-ISS all_signal.iss all_signal
Number_of_terminals=8
1 Pin_I/O pin_name 1
2 Pin_I/O pin_name 2
3 Buffer_I/O pin_name 1
4 Buffer_I/O pin_name 2
5 Buffer_Rail signal_name VSS
6 Buffer_Rail signal_name VSSQ
|.subckt all_signal pin_1 pin_2 buf_1 buf_2 Buf_VSS Buf_VSSQ
| W1 pin_1 Buf_VSSQ buf_1 Buf_VSSQ N=1 L=.5 RLGCmodel= ...
| W2 pin_2 Buf_VSS buf_2 Buf_VSS N=1 L=.5 RLGCmodel= ...
|.ends all_signal
[End Interconnect Model]
[End Interconnect Model Set]
[Interconnect Model Set] Set2
[Interconnect Model] DQ
File_IBIS-ISS DQ.iss DQ
Number_of_terminals=3
1 Pin_I/O pin_name 1
2 Buffer_I/O pin_name 1
3 Buffer_Rail signal_name VSSQ
|.subckt DQ pin_1 buf_1 ref
| W1 pin_1 ref buf_1 ref N=1 L=.5 RLGCmodel= ...
|.ends DQ
[End Interconnect Model
[Interconnect Model] CMD
File_IBIS-ISS CMD.iss CMD
Number_of_terminals=3
1 Pin_I/O pin_name 2
2 Buffer_I/O pin_name 2
3 Buffer_Rail signal_name VSS
|.subckt CMD pin_2 buf_2 ref
| W1 pin_2 ref buf_2 ref N=1 L=.5 RLGCmodel= ...
|.ends CMD
[End Interconnect Model
[End Interconnect Model Set]
[Interconnect Model Set] Set3
[Interconnect Model] DQ
File_IBIS-ISS DQ.iss DQ
Number_of_terminals=3
1 Pin_I/O pin_name 1
2 Buffer_I/O pin_name 1
3 A_gnd
|.subckt DQ pin_1 buf_1 ref
| W1 pin_1 ref buf_1 ref N=1 L=.5 RLGCmodel= ...
|.ends DQ
[Interconnect Model] CMD
File_IBIS-ISS CMD.iss CMD
Number_of_terminals=3
1 Pin_I/O pin_name 2
2 Buffer_I/O pin_name 2
3 A_gnd
|.subckt CMD pin_2 buf_2 ref
| W1 pin_2 ref buf_2 ref N=1 L=.5 RLGCmodel= ...
|.ends CMD
[End Interconnect Model
[End Interconnect Model Set]
[Interconnect Model Set] Set4
[Interconnect Model] all_signal_A_gnd
File_IBIS-ISS all_signal_A_gnd.iss all_signal_A_gnd
Number_of_terminals=8
1 Pin_I/O pin_name 1
2 Pin_I/O pin_name 2
3 Buffer_I/O pin_name 1
4 Buffer_I/O pin_name 2
5 A_gnd
|.subckt all_signal_A_gnd pin_1 pin_2 buf_1 buf_2 ref
| W1 pin_1 ref buf_1 ref N=1 L=.5 RLGCmodel= ...
| W2 pin_2 ref buf_2 ref N=1 L=.5 RLGCmodel= ...
|.ends all_signal_A_gnd
[End Interconnect Model]
[End Interconnect Model Set]
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
978.461-0449 x 133
Mobile 303.335-6156
From: Walter Katz <wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>>
Sent: Friday, March 16, 2018 9:40 AM
To: 'IBIS-Interconnect'
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>
Subject: Question to Randy and MM
Randy, MM,
We all know (at least by inference) that both Intel and Micron do Power Aware
Analysis on their components. (Notice I use the word Analysis which could be
Simulation or any of a number of other techniques reported in the literature.)
We also know that Micron delivers Power Aware IBIS files. At least one FPGA
company also supplies Power Aware IBIS files.
Can either Randy or MM state that the current BIRD 189 syntax allow EDA tools
to build Power Aware simulations for IBIS Power Aware [Models]?
* Brad has told me that the BIRD 189 syntax can represent Power Aware
package models that work correctly in his simulator, although they require that
other Interconnect Models in the channel need to follow certain rules (e.g.
never using Node 0).
Can either Randy or MM state that when using Power Aware on-die or package
models if they:
1. Use a single "reference node", or if the reference nodes are distributed?
2. If a single "reference node" is it Node 0, or the signal name at the pins?
3. If the reference node is not Node 0, then do they require or Board
interconnect to not allow Node 0.
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
978.461-0449 x 133
Mobile 303.335-6156
Attachment:
ReferencingProblems_2018_03_21.pdf
Description: ReferencingProblems_2018_03_21.pdf
