[ibis-macro] Re: IBIS-ATM teleconference - Agenda for February 23, 2021

  • From: "Hwang, Chulsoon" <hwangc@xxxxxxx>
  • To: "wkatz@xxxxxxxxxxxxx" <wkatz@xxxxxxxxxxxxx>, "fangyi_rao@xxxxxxxxxxxx" <fangyi_rao@xxxxxxxxxxxx>, "bob@xxxxxxxxxxxxxxxxx" <bob@xxxxxxxxxxxxxxxxx>, "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
  • Date: Tue, 2 Mar 2021 17:06:30 +0000

Hi Walter,

Thanks for your feedbacks. I wanted to clarify that a new keyword will define 
the propagation delays (only propagation delays) with the rail variation 
instead of the delay variation in seconds/volt. Combining with Ku/Kd, this 
should be able to cover the jitter sensitivity in multiple frequency range and 
also multi-tone power noise case. Especially, jitter sensitivity as a constant 
number defined in seconds/volt variation wouldn’t be able to provide a 
capability to handle multi-tone power noise cases. Let me try to make this 
point clear in today’s meeting.

For the clock forwarded system you mentioned, I am not familiar with the 
systems, but as the delay variations can be embodied into Ku/Kd during 
simulation, I expect that a simulator can do actual simulations of data along 
with clock and measure this effect in simulations.

Best regards,
Chulsoon

From: ibis-macro-bounce@xxxxxxxxxxxxx <ibis-macro-bounce@xxxxxxxxxxxxx> On 
Behalf Of Walter Katz
Sent: Tuesday, March 2, 2021 8:34 AM
To: fangyi_rao@xxxxxxxxxxxx; Hwang, Chulsoon <hwangc@xxxxxxx>; 
bob@xxxxxxxxxxxxxxxxx; ibis-macro@xxxxxxxxxxxxx
Cc: Sun, Yin (S&T-Student) <ysc26@xxxxxxx>
Subject: [ibis-macro] Re: IBIS-ATM teleconference - Agenda for February 23, 2021

Chulsoon,

I want to focus on what you want the simulators to do, and how engineers would 
use the results of these simulations to make engineering decisions.

The premise is that changes to the rail voltage will affect internal path 
delays and therefor cause changes in the time that drivers transition. The 
affect on the performance of a channel is a function of the magnitude and 
spectral density of the rail voltage variations and the differences between 
clock and data paths.

I presume that you will be suggesting a new IBIS keyword (Rail_Induced_Delay) 
that will define the delay variation of a driver as a function of the 
difference of the rail voltage. I live in a linear world, so I would express 
this in Seconds/Volt (e.g. 5ps/30mV). I also presume that you would expect a 
simulator to insert a voltage controlled delay element between the stimulus and 
the input to the IBIS Tx model. The voltage input to the delay element would be 
the difference between the instantaneous voltage supplied to the IBIS model and 
the Pullup Reference Voltage.

For clock forwarded systems (e.g. DDR4 and DDR5), the differences in the clock 
and data delay paths in the Tx will introduce jitter both because of this 
affect. One can choose to measure this affect using simulation, or just by 
knowing the magnitude of this affect and know the power supply spectral 
density, one can calculate the amount of jitter introduced.

Are you proposing something like using the value of Rail_Induced_Delay to allow 
engineers to determine the amount of timing margin lost as a function of 
spectral density, or actually doing simulations of data along with clock to 
measure this effect in simulations.

Do component data books document the magnitude of  Rail_Induced_Delay for their 
chip, or do standards require that in order to be compliant, they put a 
compliance test limit on Rail_Induced_Delay?

Walter
​​​​​
Walter Katz
Work  508.647-7633
Cell      720.417-3762
[Description: Description: Visit MathWorks.com]


From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx
<ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx>> On 
Behalf Of Fangyi Rao
Sent: Tuesday, March 2, 2021 5:28 AM
To: hwangc@xxxxxxx<mailto:hwangc@xxxxxxx>; 
bob@xxxxxxxxxxxxxxxxx<mailto:bob@xxxxxxxxxxxxxxxxx>; 
ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>
Cc: Sun, Yin (S&T-Student) <ysc26@xxxxxxx<mailto:ysc26@xxxxxxx>>
Subject: [ibis-macro] Re: IBIS-ATM teleconference - Agenda for February 23, 2021

Hi Chulsoon,

Thanks for the presentation. I have some questions regarding slide #10.


  1.  Is Time missing in the Vcc equations?
  2.  Is 1e6 the Vcc frequency in Hz?
  3.  In the two sinusoidal illustrations do the red lines (with double arrows) 
represent the time average of a switch? If so, then the illustration is 
misleading because the Vcc period is much longer than the rise/fall time.
  4.  Are Time values in the two lower plots of rise edge the same as Time 
value in the Vcc equations? If so, then the left and right rise edges are not 
triggered at the same time and therefore experience different Vcc variations.

I also want to point out that because the Vcc period is much longer than the 
rise/fall time, the difference between the two cases (with different Vcc 
phases) is a DC effect but not a dynamic effect.

Best regards,
Fangyi

From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx
<ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx>> On 
Behalf Of Hwang, Chulsoon
Sent: Wednesday, February 24, 2021 5:22 PM
To: bob@xxxxxxxxxxxxxxxxx<mailto:bob@xxxxxxxxxxxxxxxxx>; 
ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>
Cc: Sun, Yin (S&T-Student) <ysc26@xxxxxxx<mailto:ysc26@xxxxxxx>>
Subject: [ibis-macro] Re: IBIS-ATM teleconference - Agenda for February 23, 2021


CAUTION: This message originates from an external sender.
Bob,
Thanks for the feedbacks. We will correct them in our final submission.

Curtis,
The presentation slides from Tuesday’s meeting are attached.

Best Regards,
Chulsoon

From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx
<ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx>> On 
Behalf Of Bob Ross
Sent: Wednesday, February 24, 2021 6:41 PM
To: Hwang, Chulsoon <hwangc@xxxxxxx<mailto:hwangc@xxxxxxx>>; 
ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>
Subject: [ibis-macro] Re: IBIS-ATM teleconference - Agenda for February 23, 2021

Hi Chulsoon,

Thank you for your interesting presentation and paper.  We look forward to 
having more discussion.

One minor correction: the most recent IBIS Specification link for [4] is now at:

http://www.ibis.org/ver7.0/ver7_0.pdf<https://nam02.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefense.com%2Fv3%2F__https%3A%2Fnam02.safelinks.protection.outlook.com%2F%3Furl%3Dhttp*3A*2F*2Fwww.ibis.org*2Fver7.0*2Fver7_0.pdf%26data%3D04*7C01*7C*7Cae7764a1d0f24783c6ce08d8d9260783*7Ce3fefdbef7e9401ba51a355e01b05a89*7C0*7C0*7C637498105263144024*7CUnknown*7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0*3D*7C3000%26sdata%3D8x20yAdJcU0NRNIaIDlzaZ2cFY3SvYyW2N01PERUTRk*3D%26reserved%3D0__%3BJSUlJSUlJSUlJSUlJSUlJSU!!I5pVk4LIGAfnvw!1Ry-8jlecwwhi7BhNCJVfFvEK3lw3qBDXXvBhNcG80BdIszHBg4xiQFhorkVZ5feDms%24&data=04%7C01%7C%7C17c7b86929d04a2aaacb08d8dd884242%7Ce3fefdbef7e9401ba51a355e01b05a89%7C0%7C0%7C637502925301223306%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=6CK2YowI5t%2FfxoFM0Dsq14T0OrIQDtPIzNZg4ErMRHQ%3D&reserved=0>

The other links are correct.  IBIS is no longer hosted by the 
www.eda.org<https://nam02.safelinks.protection.outlook.com/?url=https%3A%2F%2Furldefense.com%2Fv3%2F__http%3A%2Fwww.eda.org__%3B!!I5pVk4LIGAfnvw!1Ry-8jlecwwhi7BhNCJVfFvEK3lw3qBDXXvBhNcG80BdIszHBg4xiQFhorkVNUtwJEk%24&data=04%7C01%7C%7C17c7b86929d04a2aaacb08d8dd884242%7Ce3fefdbef7e9401ba51a355e01b05a89%7C0%7C0%7C637502925301233302%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=fwOV85vM2GEH6iUWQvBFVjXhQBwQzow5LwJ9t8WiFLw%3D&reserved=0>
 URL.

----

Also the authors for reference [10] should be corrected to Y. Sun and Y. Dai.

Best Regards,
Bob

From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Hwang, Chulsoon
Sent: Wednesday, February 24, 2021 6:54 AM
To: ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>
Subject: [ibis-macro] Re: IBIS-ATM teleconference - Agenda for February 23, 2021

Dear ATM Task group,

Thanks for the feedbacks yesterday and it was a great discussion!
Attached please find the paper about the PSIJ modeling in IBIS.
This paper has been submitted to the IEEE EMC+SIPI symposium 2021 and is under 
review now.

Regards,
Chulsoon

From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx
<ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx>> On 
Behalf Of Muranyi, Arpad
Sent: Tuesday, February 23, 2021 11:18 AM
To: ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>
Subject: [ibis-macro] IBIS-ATM teleconference - Agenda for February 23, 2021

Time:  Tuesday, February 23, 2021 at Noon US Pacific Time
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Agenda
======

1)  Opens
2)  Roll call
3)  Review of ARs:

Arpad and Ambrish:  Suggest a better name for Use_New_Flow
         - done (Arpad suggested a parameter name for Fangyi in a
           private email before Fangyi submitted the BIRD to the
           IBIS Open Forum).

Any other AR-s?


4)  Call for any IBIS related patent disclosures
5)  Approval of minutes


6)  Supporting PI modeling/simulation in IBIS               (Zhiping)
    - introducing a new BIRD by Chulsoon (Hwang)


7)  BIRD210 New Redriver AMI Flow                            (Fangyi)
    - discussion (requested by the IBIS Open Forum)


8)  Clarification for PAM4 threshold                         (Hansel)
    - introduce/discuss a new BIRD draft


9)  GDDR6x signaling update                                   (Randy)
    - update?


10) Motion to adjourn?


Topic bin list:
===============

- Parameter directionality summary (Mike M.)
- Removing the single-ended input threshold requirements for
  differential buffers  (Mike M.?)
- Removing the single-ended characterization load requirements for
  differential buffers  (Mike M.?)
- Fix all the referencing problems in the current specification
  (after Randy’s C_comp proposal and BIRD189 are done)
  (BIRD181.1 Bob, Mike L.)
- Guidance for power-aware vs. AMI models – do we have rules for
  how a power-aware (and therefore potentially non-LTI) buffer
  analog data set should be used with IBIS-AMI algorithmic data?
  (important topic - 2018 ASIA IBIS Summit presentations)
  (the spec. may not need to be changed for this)
- Digital signing of DLL/SO files.  Should it be mentioned in the
  spec, or required?


Tabled ARs:
===========


Tabled topics:
==============

11) Old Redriver flow proposals/BIRDs
    a) Intel’s Redriver Flow presentation                     (Intel)
    b) 166.4  Resolving problems with Redriver Init Flow     (Walter)
    c) BIRD190                                              (Ambrish)
    d) Fangyi’s (old) Redriver flow BIRD draft               (Fangyi)
       - add equations
       - consider rewriting the AMI "front end" in the spec (flows)
         (when this proposal is added to the spec)


12) Support for RDL in IBIS                                 (Walter)


13) Jitter HF/LF components and Jitter Amplification       (Mike M.)


14) Other DDR5 related topics
    - rise fall asymmetry


15) New BIRDs from Editorial Task Group?                  (Bob/Radek)
    a) Specify buffer reference terminals for pins ([Pin Reference])
    b) Simulation (aka DIA) vs. DUT (depends on #a)
    c) C_comp and package reference in simulation clarifications
       (depends on #a)
    d) Make changes to the [Receiver Threshold], once a) and b) are
       resolved


16) How to handle missing min/max data?                       (Arpad)
    - what should be the governing rule for synchronizing
      typ/min/max data?


Pending BIRDs awaiting discussion:
==================================

166.4  Resolving problems with Redriver Init Flow
190    Clarification for Redriver Flow
TBD    New proposal for Redriver Flow (may replace BIRD166)

Thanks,

Arpad
=====================================================================

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