[ibis-macro] Ground Clarification, why it is so confusing ... VinL, VinH, Data Derivation, Test Fixture Ground, Absolute Ground, ...

  • From: Walter Katz <wkatz@xxxxxxxxxx>
  • To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx>
  • Date: Mon, 18 Jan 2016 07:43:14 -0500 (EST)

All,



I think I figured it out. First, IBIS is a measurement specification. All
of the numbers in IBIS are derived from measurements, and IBIS describes
how those measurements are made, not how those measurements are used!!!!



IBIS does not describe how an IBIS model is connected in a system. If IBIS
did, it would have something like the following:











































































One other confusion within IBIS is the description of A_gnd defined in
[External Model] on page 94 of Ver 6.1:



A_gnd is a universal reference node, similar to SPICE ideal node "0."



This artifact was created because [External Model] has both digital and
analog ports:



The multi-lingual modeling extensions maintain and expand this approach,
assuming that both digital signals and/or analog signals can move to and
from the model unit. All VHDL-AMS and Verilog-AMS models, therefore, must
have digital ports and analog ports. In certain cases, digital ports may
not be required, as in the case of interconnects; see [External Circuit]
below. Routines to convert signals from one format to the other are the
responsibility of the model author.

Digital ports under AMS languages must follow certain constraints on type
and state. In VHDL-AMS models, analog ports must have type "electrical".
Digital ports must have type "std_logic" as defined in IEEE Standard
Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164),
or later. In Verilog-AMS models, analog ports must be of discipline
"electrical" or a subdiscipline thereof. Digital ports must be of
discipline "logic" as defined in the Accellera Verilog-AMS Language
Reference Manual Version 2.2, or later and be constrained to states as
defined in IEEE Std. 1164-1993, or later.

The digital ports delivering signals to the AMS model, D_drive, D_enable,
and D_switch, must be limited to the '1' or '0' states for VHDL-AMS, or,
equivalently, to the 1 or 0 states for Verilog-AMS. The D_receive digital
port may only have the '1', '0', or 'X' states in VHDL-AMS, or,
equivalently, the 1, 0, or X states in Verilog-AMS. All digital ports
other than the foregoing predefined ports may use any of the logic states
allowed by IEEE Std. 1164-1993, or later.

SPICE, IBIS-ISS, VHDL-A(MS), Verilog-A(MS) versus VHDL-AMS and
VERILOG-AMS:

SPICE, IBIS-ISS, VHDL-A(MS), Verilog-A(MS) cannot process digital signals.
All SPICE, IBIS-ISS, VHDL-A(MS), Verilog-A(MS) input and output signals
must be in analog format. Consequently, IBIS multi-lingual models using
SPICE, IBIS-ISS, VHDL-A(MS) or Verilog-A(MS) require analog-to-digital
(A_to_D) and/or digital-to-analog (D_to_A) converters to be provided by
the EDA tool. The converter subparameters are declared by the user, as
part of the [External Model] or [External Circuit] syntax, with
user-defined names for the ports which connect the converters to the
analog ports of the SPICE, IBIS-ISS, VHDL-A(MS), or Verilog-A(MS) model.
The details behind these declarations are explained in the keyword
definitions below.

The electrical output characteristics of D_to_A converters are equivalent
to ideal voltage sources having a zero ohm output impedance, and the
electrical input characteristics of A_to_D converters are equivalent to
ideal voltage probes, having an infinite input impedance.

To summarize, Verilog-AMS and VHDL-AMS contain all the capability needed
to ensure that a model unit consists of only digital ports and/or analog
ports. SPICE, IBIS-ISS, VHDL-A(MS) and Verilog-A(MS), however, need extra
data conversion, provided by the EDA tool, to ensure that any digital
signals can be correctly processed.



What is the analog value of a digital port that is either "0" or "1". That
depends on whether the EDA tool is creating a stimulus input to a driver,
or a digital output of a receiver. The digital-to-analog (D_to_A)
converter supplied by the EDA tool for the stimulus to an [Exteranl Model]
requires a reference node. This reference node should not be onfused with
the analoge reference node (e.g. VSS) that the buffer uses to connect to
the system. On page 123:



The D_to_A subparameter is followed by eight or optionally nine arguments:

d_port port1 port2 vlow vhigh trise tfall corner_name polarity

The d_port entry holds the name of the digital port. This entry may
contain user-defined port names or the reserved port names D_drive,
D_enable, and D_switch. he port1 and port2 entries hold the SPICE,
IBIS-ISS, Verilog-A(MS) or VHDL-A(MS) analog input port names across which
voltages are specified. These entries contain user-defined port names.
One of these port entries must name a reference for the other port (for
example, A_gnd).



In conclusion, IBIS is very careful about defining the reference node for
devices under test, and for interpreting and using voltage terminals on
the digital side of [External Model] and [External Circuit]. Global Ground
is only used in the context of a reference node for D/A and A/D converters
for digital signals. Absolute Ground is only used in the context of the
reference node for test fixtures.



IBIS does not state how these measurements shall be applied to simulations
where the ground clamp or power clamp reference nodes are "floating", but
it should be "self-evident" that only the voltage between the I/O buffer
pad and it's local ground clamp or power clamp reference node.





Walter





From: Walter Katz [mailto:wkatz@xxxxxxxxxx]
Sent: Friday, January 15, 2016 11:45 PM
To: IBIS-ATM <ibis-macro@xxxxxxxxxxxxx>
Subject: VinL, VinH, Data Derivation, Test Fixture Ground, Absolute
Ground, ...



All,



There seems to be some controversy of the reference node that needs to be
used in conjunction with IBIS Model levels such as VinL and VinH. One of
the sources of confusion is how to setup a Device Under Test (DUT). I
believe that one of the rail voltages connected to the buffer must be the
reference node, and generally this is either the pulldown rail or ground
clamp rail terminal of the buffer (what IBIS calls the common ground pin
terminal). In several places in IBIS (see for example page 72 of IBIS 6.1,
see below). I think the first paragraph should have been:



Figure 16 illustrates a general configuration from which a [Rising
Waveform] or [Falling Waveform] is extracted. The DUT die shows all of the
available power and ground pin reference voltage terminals. For many
buffers, only one power pin and one common ground pin terminal are used.
The absolute GND common ground pin is the reference for the V_fixture
voltage and the package model equivalent network. It can also serve as a
reference for C_comp, unless C_comp is optionally split into component
attached to the other reference voltages.



The picture should use "GND" or "VSS" instead of the Earth Ground Symbol
(as it was when the IBIS spec did not have graphics).



For Test Fixture voltage measurements to make any sense, they must be
referenced to the common ground pin terminal. In any event, absolute
ground here only refers to the Test Fixture reference. Concluding from
this description of how to hook up a test fixture to the statement that
all simulation waveform measurements when the common ground pin is hooked
up to a floating ground requires that the EDA tool evaluates the waveform
of the I/O pin referenced to the common ground pin terminal. Note that
IBIS can choose Si_location and Timing_location at the Pin or Die. If
these locations are at the Die, then the I/O waveform must be reference to
the common ground die terminal.







Page 72



Figure 16 illustrates a general configuration from which a [Rising
Waveform] or [Falling Waveform] is extracted. The DUT die shows all of the
available power and ground pin reference voltage terminals. For many
buffers, only one power pin and one common ground pin terminal are used.
The absolute GND is the reference for the V_fixture voltage and the
package model equivalent network. It can also serve as a reference for
C_comp, unless C_comp is optionally split into component attached to the
other reference voltages.

The [Composite Current] I-T table includes all of the current through the
[Pullup Reference] terminal. If the [POWER Clamp Reference] terminal is
the same as the [Pullup Reference] terminal (according to the [Pin
Mapping] keyword table), the [Composite Current] entries include the
currents through both the [POWER Clamp] and [Pullup] sections of the DUT
(for example, when an on-die terminator is connected to the power
reference terminal). Note that the terminals are shown in terms of
separately defined reference voltages, but still exist even if they are
defined with default [Voltage Range] or 0 V settings.





Figure 1- [External Reference] - (used only for non-driver modes)





Walter Katz

<mailto:wkatz@xxxxxxxxxx> wkatz@xxxxxxxxxx

Phone 303.449-2308

Mobile 303.335-6156

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  • » [ibis-macro] Ground Clarification, why it is so confusing ... VinL, VinH, Data Derivation, Test Fixture Ground, Absolute Ground, ... - Walter Katz