Walter,
I have a hopefully simple question:
If all 100 of these 6 terminal models are in one Group, and I want to run a
simulation with that Group and all 100 pins. How do you connect up those 6
terminal models in a netlist for all 100 pins? I am just wondering how do
handle the overlap of models.
For instance, your model Pin_1 has terminals Pin 2 and Pad 2 as Aggressors.
Model Pin_2 would also have Pin 2 and Pad 2 but as a Victim. And model Pin_3
would have terminals Pin 2 and Pad 2 as Aggressors. How do you connect models
Pin_1, Pin_2, and Pin_3 considering the overlapping of the terminals?
Thanks,
Justin
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx] ;
On Behalf Of Walter Katz
Sent: Wednesday, December 13, 2017 9:20 AM
To: IBIS-Interconnect <ibis-interconn@xxxxxxxxxxxxx>; IBIS-ATM
<ibis-macro@xxxxxxxxxxxxx>
Subject: [EXT] [ibis-macro] FW: "Aggressors"
From: Walter Katz [mailto:walter.m.katz@xxxxxxxxx]
Sent: Wednesday, December 13, 2017 10:02 AM
To: 'IBIS-Interconnect'
<ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>>
Subject: "Aggressors"
All,
For our discussion about Aggressor rules in Groups, I would like us to consider
the following common example:
Consider a 100 pin component (for simplicity I am assuming that all 100 pins
are I/O and they are numbered from 1 to 100. Routing is done on one layer, and
each pin has 99% of its crosstalk from the connection on the pin on either
side. The package layout tools generates 100 Models, one for each pin. Each
Model has 6 terminals, two terminals are the Pin and Pad of the "Victim" pin
and two "Aggressor" terminals for the Pin and Pad for the pins on either side
of the "Victim" pin. For example,
1. Model "Pin_25" would have terminals Pin 25 and Pad 25 as "Victim", and
Terminals Pin 24, Pad 24, Pin 26 and Pad 27 as "Aggressors"
2. Model "Pin_1" would have terminals Pin 1 and Pad 1 as "Victim", and
Terminals Pin 2, Pad 2, Pin 100 and Pad 100 as "Aggressors"
3. Model "Pin_100" would have terminals Pin 100 and Pad 100 as "Victim",
and Terminals Pin 1, Pad 1, Pin 99 and Pad 99 as "Aggressors"
Every I/O pin has one Model with its terminals as a Victim, and two Models with
its terminals as Aggressors.
I claim that this should not generate any errors or warnings.
Does anyone disagree?
Walter
