I think this conversation is going in the wrong direction, and
as far as the original question goes (what is the reference of
the S-parameter model) it is really irrelevant whether the chip
has a GND pin or not.
Let’s review the original question again. This time I will rephrase
it a little differently based on some of the conclusions we made
in the conversations so far.
If the package and/or on-die interconnect is modeled with an
S-parameter model which has as many ports as the number of pins
(or pads, or buffer terminals) on the device, what should be the
reference terminal of the S-parameter model connected to? (The
way I worded this question implies that there are no more pins,
pads or buffer terminals available on the device for the possibility
to connect the reference terminal to it).
In one of your earlier emails you described how S-parameters are
measured in the lab. Put a probe on a pin/pad/buffer terminal
that is being measured and ground the probe to a nearby, high
quality ground. That high quality ground may be something other
than a GND pin/pad/buffer terminal of the device itself. If this
ground connection for the probe is good enough, it may be combined
for all measurements as the common reference for all probe locations.
I would add that if it is good enough for the purpose, one may consider
it to be the node 0 “ground”. In this case, the reference node of
the S-parameter model can simply be connected to node 0.
On the other hand, you can make the measurements so that the probe
reference is connected to one of the pins for all probe locations.
(This can be a GND, Vcc, or even a signal pin, although that would
be kind of a crazy thing to do). In this case the S-parameter model
will have NumberOfPins-1 ports.
One of the examples we discussed, where the 4-port S-parameter model
only contains the signal lines of a differential pair, may be referenced
to anything if all of the probe locations are referenced to that one
location. This could be a +Vcc pin/pad, a –Vcc pin/pad (or even a
signal pin, although that would be kind of a crazy thing to do).
But, as Brad pointed out, there is an additional problem with these
kinds of models, because the parasitics of the power and ground traces
has to be included in the signal’s model, but that is a different
question from where the reference terminal should be connected to.
So as far as finding data sheets for devices which do not have GND pins,
I think we are vesting our time. That is really not the question here.
For the same reason, I think your proposed text really shouldn’t deal
with [Pin Mapping] and signal names or reserved model names to determine
what the reference terminal of the S-parameter model should be connected
to. I think it should simply be connected to node 0, or any other ideal
DC voltage the simulator prefers to use.
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
On Behalf Of Walter Katz
Sent: Monday, February 29, 2016 4:23 PM
To: Tom Dagostino; mlabonte@xxxxxxxxxx
Subject: [ibis-macro] Re: Determining the reference signal_name of an I/O buffer
Thank you for find this part. Can you tel me the IC Vendor and a vendor part
number so that I can look at their data sheet. Since they are measuring
voltages, I would like to know how they indicate what is the reference pin for
the voltages that are being measured.
From: Tom Dagostino [mailto:tom@xxxxxxxxxxxxxxxxx]
Sent: Monday, February 29, 2016 2:48 PM
Cc: 'IBIS-ATM' <ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>
Subject: RE: [ibis-macro] Re: Determining the reference signal_name of an I/O
If you look at ECL chips you will find there is no GND in them. There is a Vee
and a Vcc. One common way of connecting ECL chips is to have Vcc at 2V and Vee
at -3.2 or -1.3V. Enclosed is an example test circuit. There are no pins with
GND in this chip. The input and output voltages are specified as Vcc – Xspec.
I’ve also worked with serial data chips that have magnetic coupling between the
input stage and the output stage. The output stage is meant to float with
respect to the input. Think about a communications link between two different
buildings where there are two different “grounds” with distinctly different
voltages on them. We cannot state the output high voltage is 3.3V when
measured at the input reference GND. It may be 1,603V, or -2,163.4V. Yes, you
can tie the two grounds together and you can have local “grounds”. But within
the confines of an IBIS model GND1 is not GND2. See ADM2486.
And while we are at it there is a whole class of other serial communication
chips that generate their own voltages internally. The parts are power by a
3.3V supply but the output has to swing from say -5V to +5V. There are voltage
doublers in these chips with flying capacitors. There is no hard fixed supply.
The output impedance of these supplies is not very low.
And there is another class of chips that have internal LDOs built into them.
And I’m seeing more and more of these. The pullup and Powerclamp references
are not power supplies on the board. For example in one recent part there was
a single 3.3V supply to the chip. Some of the output and input buffers worked
off the 3.3V supply. But other worked off an internally generated 1.8V supply.
And one chip recently had 3.3V and 1.8V supplies. One set of output buffers
could work directly off the 3.3V supply or they could be switched to an
internally generated 2.1V supply.
One of the assumptions all SI simulators make is the supply can both sink and
source current. In a large board this works fine for SI purposes because there
are enough current sinks on the board that any part whose power clamp is
supplying current to the supply has a place for this current to flow. But with
these local LDO features any overshoot causing a Powerclamp to conduct will
upset the local supply. There is usually a pin in these LDO based chips to
bypass the supply, but not always.
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Mike LaBonte
Sent: Sunday, February 28, 2016 8:36 PM
Subject: [ibis-macro] Re: Determining the reference signal_name of an I/O buffer
I think we need to be clear at all times whether it is sufficient to identify a
reference signal_name or if an exact pin must be identified. The first sentence
of this goes both ways. One question is whether the parasitics of the
interconnect shorting the pins associated with one signal together are small
enough to warrant claiming that it wouldn't matter which of those pins were
used as a measurement reference node. I'm not so sure, particularly if package
parasitics are in play.
A potential conflict might come up with BIRD 161.1 Supporting Incomplete and
Buffer-only [Component] Descriptions<http://ibis.org/birds/bird161.1.docx>. It
has not yet passed, but it proposes allowing the first column of [Pin] to give
pad names instead of pin names. At least in that case we would know pin
parasitics were absent. But it allows says that a [Pin] section could have just
IBIS has always supported producing models from hardware measurement, but it is
not certain that IBIS requires models to be expressed as though hardware had
been measured when it wasn't. A quick search tells me I have 169 IBIS files on
hand that do not contain the word "GND".
From: "Walter Katz" <wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>>
To: "IBIS-ATM" <ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>
Sent: Sunday, February 28, 2016 12:08:20 PM
Subject: [ibis-macro] Determining the reference signal_name of an I/O buffer
Continuing this thought, since IBIS is a component measurement based system,
and since measurement are made at the pin of a component, and since every
measurement at an I/O pin is made between that pin and some nearby reference
pin, then all we need to do is define a method of determining the reference
signal_name for every I/O pin. The following algorithm should work for all
known existing IBIS models:
1. [Pin Mapping] tells the bus_label on each of the buffer rail terminals.
2. These bus_labels define the signal_name on each of the rail terminals.
3. If just one signal_name is on a Pin with Model_name GND, and the
values of the Pullup Reference, Power Clamp Reference, Ground Clamp Reference,
Pulldown Reference assigned that has that signal_name has a value of 0.0V in
the [Model], then a pin of that signal_name near the I/O pin is the reference
for the measurements at the I/O pin. Similarly, the I/O buffer rail terminal
with the reference signal_name at the I/O buffer is the reference node for
measurements at the I/O buffer. Similarly, the supply pads at the die/package
boundary near the I/O die pad are the reference for measurements at the I/O die
If this algorithm does not work for an I/O buffer (and I claim such a case does
not exist) then we can enhance IBIS by adding an option [I/O Reference] section
that has two columns. The first column is the Pin_name of an I/O buffer, and
the second column is the signal_name of the reference for all measurements at
the I/O buffer.
From: Walter Katz [mailto:wkatz@xxxxxxxxxx]
Sent: Saturday, February 27, 2016 8:58 PM
To: IBIS-ATM <ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>
Subject: One of the rail voltages of every IBIS buffer is a GND signal_name and
a reference node.
I have looked at the data sheets for parts with RS232, ECL, PECL and MECL
buffers, and every one of them has one of the rail voltages connected to a
Ground (GND) data book name (signal_name).
Although the IBIS standard does allow the user to associate all of the rail
voltages with bus_labels on POWER pins, such a buffer is an unnatural act.
If we state that it is a given that every buffer has a Ground rail connection,
then we can state that every buffer has a well-defined reference node for every
other terminal measurement at the buffer.
I challenge anyone on this committee to find a part with an I/O buffer that has
no rail terminals that are Ground.