[ibis-macro] Comments on the macro library documentation
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: "ibis-macro" <ibis-macro@xxxxxxxxxxxxx>
- Date: Fri, 7 Jul 2006 09:39:16 -0700
Mike,
Here are my first pass comments on the documentation in the
VHDL-AMS version of the macro library. Most of them are cut
and paste problems and occur multiple times. I suspect many
of them appear in the Verilog-A(MS) version also, although I
must admit, I didn't look at that one yet. Please make sure
that the editorials are absolutely clean before posting it
again. I would prefer not to have to deal with such obvious
mistakes (and so many of them), I have spent enough time on
writing the code... :-) It would be nice if others on this
list could help you proof read this if you need help with this.
There are also a few technical ones. I tried to describe them,
but we may need to work more on that together to make them clean.
Thanks,
Arpad
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Documentation comments on the VHDL-AMS version of the macro library:
1) Make separator lines the same length as others. I like attractive
appearance.
2) "Module" in VHDL-AMS is called "entity" (or "architecture"), what should
we call them then in the comments?
3) "moduledoc" has no space around it, and is not capitalized
as "Module list", and is in one word, instead of two. I would prefer
a similar style as "Module list" for appearance reasons. I am a stickler
on that.
4) Instance call examples in VHDL-AMS library should not show Verilog-AMS
syntax!
5) What is the purpose of the SPICE instance call example using X1?
Is this supposed to show HSPICE's Verilog-A call?
6) In the VCR model we could mention that:
"The sense terminals ps and ns draw no current" as in other voltage
controlled sources.
7) Start a new paragraph for "This is a charge conserving model." in VCC.
8) Start a new paragraph for "This is a flux conserving model." in VCL.
9) Do not use the "\" at the end of the VAMS example lines, it is
incorrect syntax.
10) Starting with VCVS, the terminal p and n are described as resistor
terminals which is incorrect...
11) The CCVS_MIN description should be changed to current controlled.
12) The VCVS_MAX description's equation says "min".
13) The CCVS_MAX description should say that the sense terminals are short.
14) Starting with CCVS_MAX there are no instance call examples.
15) The divider elements have another parameter "ZeroLimit" which is not
described. When the absolute value of the divisor is less than that,
we are using another equation to prevent going to infinity, i.e. div/0.
16) The PWL sources work a little different between the VHDL-AMS and Verilog-A
versions. In VHDL-AMS we have an optional file name parameter and if the
file exists we can read the tables from the file too. Also in the VHDL-AMS
version we do not have the length parameter, but we have another one,
called
Max_lenght. We will have to work on this a little more to get the correct
description.
17) In the event controlled PWL sources the threshold logic was changed a
little.
At DC, it will start in the high state if the input is greater than the
average of the two threshold values and low otherwise. At each subsequent
transition, it will go high if input is greater than the Vth_R and low if
it is less than or equal to Vth_F.
18) VCCS description equation incorrect, it should be I() = V() * Scale
19) CCCS_DELAY equation doesn't show the delay part.
20) CCCS_MIN description wrong.
21) VCCS_MAX equation wrong.
22) CCCS_MAX equation wrong.
23) VCCS_ABS equation wrong.
24) CCCS_ABS equation wrong.
25) VCCS_SUM equation wrong.
26) CCCS_SUM equation wrong.
27) VCCS_MULT equation wrong.
28) CCCS_MULT equation wrong.
29) VCCS_DIV equation wrong.
30) CCCS_DIV equation wrong.
31) IBIS_*** buffer models: Max_dt description not good. It doesn't control
the simulation time step. What it does, it tell the model to resample the
Vt tables at this resolution. It will insert points in the table if the
data is spaced at larger dt.
There are two thresholds instead of Vth, we have now Vth_R and Vth_F. To
be
compatible with HSPICE, at DC the output will be high if the input is >
than
the average of Vth_R and Vth_F and low otherwise. At every subsequent
transition
it will go high if the input becomes > than the Vth_R and it will go low
if the
input is < Vth_F. And I just found an inconsistency between these and the
PWL
sources where this was <=.
If there is an enable signal, the input threshold will behave as at t=0
when
the buffer goes from 3-state to enabled in terms of the input thresholds
are
concerned. The enable signal behaves the same as the input signal with
respect
to the thresholds.
We also have an optional file name parameter in the VHDL-AMS version to be
able
to read the data from a file. If the data exists in the file that will
override
all other parameters passed in on the calling statement. If it doesn't,
it will
take the data passed in. If nothing is passed in, it will take the
internal
defaults. (This is also true at the PWL sources).
32) TRISTATE buffers do not have Vinh and Vinl.
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