[ibis-macro] Comment on the minutes of the last meeting

  • From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
  • To: <ibis-macro@xxxxxxxxxxxxx>
  • Date: Mon, 20 Nov 2006 12:49:27 -0800

As I was reading the minutes of the last IBIS-ATM teleconference, I
noticed this line:

"Todd: Cadence prefers Verilog, Mentor prefers VHDL, others can't do both at 
all."

I need to disagree, Todd.  The tool from Dolphin, SMASH can cosimulate
VHDL-AMS, Verilog-AMS and SPICE (plus their own language called ABCD, I
believe), they can even be mixed within the same file...

Arpad
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