As I was reading the minutes of the last IBIS-ATM teleconference, I noticed this line: "Todd: Cadence prefers Verilog, Mentor prefers VHDL, others can't do both at all." I need to disagree, Todd. The tool from Dolphin, SMASH can cosimulate VHDL-AMS, Verilog-AMS and SPICE (plus their own language called ABCD, I believe), they can even be mixed within the same file... Arpad ======================================================================== --------------------------------------------------------------------- IBIS Macro website : http://www.eda.org/pub/ibis/macromodel_wip/ IBIS Macro reflector: //www.freelists.org/list/ibis-macro To unsubscribe send an email: To: ibis-macro-request@xxxxxxxxxxxxx Subject: unsubscribe