Paul, Here is the file. Try the out50v or out33v buffers. Arpad ===================================== -----Original Message----- From: Paul Fernando [mailto:prfernan@xxxxxxxx] Sent: Monday, April 10, 2006 8:45 PM To: Muranyi, Arpad Cc: ibis-macro@xxxxxxxxxxxxx Subject: Re: [ibis-macro] Another bug found in IBIS to AMS converter Arpad, Could you please send me the input IBIS file that creates the problem? Thanks, Paul On Mon, April 10, 2006 7:34 pm, Muranyi, Arpad wrote: > Paul, > > We found another bug in the converter. When we convert > a buffer type OUTPUT, the IBIS file (Lab_1.ibs) has no > clamp tables. The output of the conversion will have > zero length data which crashed out tools. > > In the Verilog output we get this: > > .IVpc_length(0), \ > .Ipc_data({}), \ > .Vpc_data({}), \ > .IVgc_length(0), \ > .Igc_data({}), \ > .Vgc_data({}), \ > > and in the VHDL output we get this: > > --------------------- > -- IV curve tables -- > --------------------- > Ipc_data > > > Vpc_data > > > Igc_data > > > Vgc_data > > > > Ipu_data > 7.05288766E+0 > 5.45121361E+0 > ... > ... > > You will need to suppress the printing of these variables > when they are zero length. > > Thanks, > > Arpad > ========================================================= > --------------------------------------------------------------------- > IBIS Macro website : http://www.eda.org/pub/ibis/macromodel_wip/ > IBIS Macro reflector: //www.freelists.org/list/ibis-macro > To unsubscribe send an email: > To: ibis-macro-request@xxxxxxxxxxxxx > Subject: unsubscribe > >