[ibis-macro] Another "Today's version" of the library

  • From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
  • To: <ibis-macro@xxxxxxxxxxxxx>
  • Date: Wed, 31 Aug 2005 15:41:15 -0700

Hello everyone,

This is another iteration of the library.  I added the
T-line, Summer, Multiplier, Divider, and Mutual inductor
to it, all of it are tested with our simulator.

I also added a list on the top to indicate what has been
done, and what needs to be or could be done.  I also added
items from Don's list which are possible candidates for
implementation (just so we don't lose track of them)...
Don's complete list with my responses is also attached to
this message.

The most important feedback I need is on what else needs
to be added to (or changed in) this library.  It would
also be nice if people could try these elements and verify
that they all work as desired.  I only tested them with
Intel's internal simulator (Lynx), and it wouldn't hurt
to check other simulators to make sure there are no crashes,
etc...  I am sure we have several people on this list do
have access to other tools which have Verilog-A...  (Am
I putting on enough pressure?  :-)

I am also planning on making a VHDL-AMS version of this
entire library soon, so stand by for a similar request
for testing on that one too.

Please review and comment.


This was the list Donald Telian gave us for the macro model
library building blocks.  Added comments to indicate what
is currently implemented in the library.


Parameter passing
AM:  This can be done with all building blocks.

Equation-based sources (voltage, current, numeric)
AM:  This cannot be done due to language limitations.  Even
     though string parameters do exist, they cannot be
     interpreted as expression (i.e. converted to "code").
     However, it would be easy to write equation based source
     statements in the templates directly assuming some
     familiarity with the language.  This could prevent or
     make the substitution of native SPICE elements impossible,

B element with c_comp on/off and table scaling (static/dynamic)
 - Hspice can?t do c_comp or dynamic
AM:  Both of these features can be added easily to the existing
     *-AMS IBIS buffer implementations.  Dynamic scaling would
     require addition control ports, as discussed with the
     controlled R, L, and C building blocks.  We need to decide
     how many and what type of control ports we want to add.

Expressions in parameters
AM:  Same answer as 2nd entry above.

Table-based PWL sources
AM:  This can be done using the $table_model keyword.  The
     problem is that currently the table or the file name
     reference to the table is hard coded, which prevents
     mutiple instances of the same exact module name to be
     used with different data tables.  There is some hope 
     that in the LRM v2.3 this will be fixed.  Until then
     manual cutting and pasting will be required.

Time-controlled sources
 - Hspice can not do
AM:  These can be implemented in *-AMS easily.  We just need to
     decide on what they should do.

If, then, else in equations
 - Hspice ???
AM:  This is easy in *-AMS.

Simulation ?time? as variable
AM:  This is easy in *-AMS.

Use of previously computed value (prev(x)) in equation
 - Hspice can not
AM:  Need to check into this how it can be done in *-AMS.

Calculation of 1st derivative of voltage or current
 - Hspice can not
AM:  This is easy in *-AMS.

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