[ibis-macro] Re: Analog Model Isolation Definition
- From: James Zhou <james.zhou@xxxxxxxxxx>
- To: Bob Ross <bob@xxxxxxxxxxxxx>, "fangyi_rao@xxxxxxxxxxx" <fangyi_rao@xxxxxxxxxxx>, "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
- Date: Fri, 23 Mar 2012 15:06:57 -0700
Hi Bob,
Thank you for clarifying the meaning of Vt and V-T in your earlier comments. My
understanding is that the parameters (such as Vt, Cc, etc.) and circuits
defined in BIRD122 are to be handled by EDA tools just as a regular IBIS-ISS
circuit the same way as any other circuit would be handled. Your first example
illustrated a way to parameterize model selection which could be a very useful
feature if added to existing Specification.
With reference to "When I use V-T, I mean the frequency response
characteristics which could be handled in many different ways - inside the
black box or as a drive voltage.", based on ATM discussions this past Tuesday,
my understanding is that the frequency response of the analog model could only
be handled inside the box. Because the conclusion of last Tuesday was that the
driver must be 0 ohm voltage source and, the load is high impedance, none of
which could influence the frequency response of the analog model. If it is
permissible by the Specification to handle the frequency response by changing
drive voltage, it needs to be clarified.
Regards,
James Zhou
QLogic Corp.
-----Original Message-----
From: Bob Ross [mailto:bob@xxxxxxxxxxxxx]
Sent: Friday, March 23, 2012 1:54 PM
To: James Zhou; fangyi_rao@xxxxxxxxxxx; ibis-macro@xxxxxxxxxxxxx
Subject: RE: [ibis-macro] Re: Analog Model Isolation Definition
Hi James:
Just a brief response at this time for clarification.
When I used Vt, I did not mean a waveform curve.
I really meant the fixed termination voltage for differential
analog model elements as in BIRD122. That could also be
called VTT or something else.
When I use V-T, I mean the frequency response
characteristics which could be handled in many different
ways - inside the black box or as a drive voltage.
I do not know the answers to most of your questions
related to processing the model in different modes or
the limitations or adjustments for these processing
modes. The tools should be doing this already, and
some tools might have different features and limitations
than others.
For various reasons, I do not know how to handle the
T-coil configuration within the proposed IBIS-AMI framework
other than as a non-ideal circuit cascaded as part of the
channel or else as a circuit moved into the TX driver.
When I tossed out *_AMS in Ex4), that may have been too far reaching
and currently irrelevant.
However, IBIS does support VHDL-A(MS) and Verilog-A(MS)
which could have analog interfaces through D_to_A converters
as with SPICE, and also parameter passing.
At this time I think we are dealing with analog stimuli which
could be ideal analog steps or waveform shapes or ramps.
Bob
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of James Zhou
Sent: Friday, March 23, 2012 11:41 AM
To: Bob Ross; fangyi_rao@xxxxxxxxxxx; ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Re: Analog Model Isolation Definition
Hi Bob,
You've raised a very important issue of "make files interchangeable between
tools". I agree with you and echo that "As long as the official
specification makes this clear, then I am satisfied". As a user of IBIS
models and EDA tools, I would further argue strongly that models SHOULD be
interchangeable between tools. In other words, proprietary implementation is
not the same thing as proprietary interpretation. The former does not
necessarily break interchangeability if done properly, but the latter often
does.
With reference to "My major conclusion is that the stimulus, parameters and
analog model would be specified as an independent group for each type of
analog model or for even IBIS buffers", if indeed this approach is adopted,
the Specification should clarify the differences between "each type of
analog model" so that they can be interchangeable between tools. Within the
context of IBIS AMI, there are two main types of independent analog models:
analog-in-analog-out(AIAO) and, logical-in-analog-out (LIAO), regardless of
the format of the model.
For example, the same T-coil circuit can be represented by RLC SPICE deck,
or S-parameter, or AMS. By hooking up the same source and load, the response
should be the same regardless of its format.
My comments on the four examples in your email (they are labeled Ex1,2,3,4
from top to bottom):
(a) Ex1,2 involve s4p and Vt curve in IBIS file. s4p is
analog-in-analog-out, IBIS Vt curve is logic-in-analog-out. Some
clarification is needed on how to mix them together. For example, how could
a logical-input be driven by an analog signal? Or if the logical-input is
not driven by anything, what is the concept of an "analog model" that only
has output but no input?
(b) Ex1,2,3 involve the "drive" of the analog model. I think the distinction
should be made between (i) the drive when deriving impulse response (ii) the
drive when obtaining Rx waveform in channel simulation. The concept of
impulse response does not apply to a logical-in-analog-out block represented
by legacy IBIS V-T curve. The specification needs to clarify such practices.
(c) Ex4 is a clear example of logical-in-analog-out, which could be a valid
example of "analog" circuit. The question is, how could such a model be
simulated with Tx IBIS AMI model? If such logical-in-analog-out blocks are
allowed by IBIS Specification, clarifications are needed on how to interpret
these data (which is different from how to implement the simulation).
Best Regards,
James Zhou
QLogic Corp.
-----Original Message-----
From: Bob Ross [mailto:bob@xxxxxxxxxxxxx]
Sent: Thursday, March 22, 2012 12:39 PM
To: fangyi_rao@xxxxxxxxxxx; James Zhou; ibis-macro@xxxxxxxxxxxxx
Subject: RE: [ibis-macro] Re: Analog Model Isolation Definition
All:
Thanks for your responses and discussion. I agree with
James Zhou below.
My major conclusion is that the stimulus, parameters
and analog model would be specified as an independent
group for each type of analog model or for even IBIS
buffers.
That makes the defined interface discussion moot since
the whole flow might be customized (and even scaled)
for each of the analog choices including s4p files.
As long as the official specification makes this clear,
then I am satisfied and does not overreach by implying
that the Analog blocks are completely interchangeable.
That is the key understanding needed make files interchangeable
between tools and also makes the scaling issue discussion
also moot.
The cookbook could follow later, both to codify existing
practices and to leave the door open to differing practices.
------
As an example of the differences and potential differences
so far:
TX: s4p - practice probably S11 = 0 (per the TI example
and some earlier historical IBM presentations) and s4p
files do not have Cc or Vt parameter (unless the parameter
is used to swap in a different s4p file. The frequency response
is in s4p file and it should be driven by a step. One vendor
could theoretically produce an s5p file with a Vt
port to pass in differential offset values. (Or Vt could
be used to swap in a different s4p file.) This should also work.
Another vendor could make the s4p file as a DC transfer and
move most of the frequency response (V-T) shaping) as a
simplified and controllable a parameterized Ramp input.
TX SPICE (or IBIS-ISS) - simplified fixed model - normally driven
by ramp waveform to approximate the source
frequency response and may have load parameters
for Cc, VT and anything else. So this is not interchangeable
with the s4p model without changing the driver and
parameters and possibly the parameter. Also, any type of
simplified model can be created with arbitrary parameters
that might be impractical with s4p TX models.
TX SPICE (or IBIS-ISS) - general TX driver - could be modeled
with a shaped frequency response and driven
by an ideal step (think Laplace transform pole-zero variables
in IBIS-ISS and isolation Op Amps (E elements)
(or cascaded Op Amps with RLC shaping networks) to configure
an extracted TX model frequency response. This would be
driven by an ideal step.
TX *_AMS models - driven by logical 0 - 1 stimulus
(only case without D_to_A converters), to produce
shaped TX responses - so the frequency shaping is
in the *_AMS model. (Not a real application yet, but
we see a lot of Verilog A embedded in SPICE models,
and this is supported in IBIS.).
Bob
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of fangyi_rao@xxxxxxxxxxx
Sent: Wednesday, March 21, 2012 11:23 AM
To: james.zhou@xxxxxxxxxx; bob@xxxxxxxxxxxxx; ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Re: Analog Model Isolation Definition
I agree with James. Spice simulations never need to make any assumption on
the values of S-parameters, and it should be same case here for IBIS analog
model specification. I don't think it's necessary to include examples of how
to treat special S-parameters. Matrix stamping of S-parameters are standard
textbook simulation techniques.
Regards,
Fangyi
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of James Zhou
Sent: Wednesday, March 21, 2012 10:53 AM
To: bob@xxxxxxxxxxxxx; 'IBIS-ATM'
Subject: [ibis-macro] Re: Analog Model Isolation Definition
Hi Bob,
Thanks for providing the link of past references. It is helpful for those of
us who were not on the list a couple of years ago.
With reference to: "the complete interface needs to be known and defined ...
to get the proper gain (S21 term).", this is a proven and well-known
principle in circuit and LTI network analysis. The conclusion at yesterday's
meeting sufficiently satisfies this requirement. The conclusion as I
interpreted was that, IBIS Specification only need to say that the Tx analog
circuit input must be driven by ideal voltage sources (i.e. zero source
impedance), and Rx analog circuit output must drive a load with infinite
impedance. Once this is established, the Specification does not need to say
anything about what goes into, or how to model, the "bigger blockbox" in the
diagram (provided it satisfies other IBIS requirements such as LTI and
IBIS-ISS compliant, etc.).
With reference to: "In both cases, the transfer function S21 term is changed
by a factor of 2...", these two cases represent total reflection by open or
short circuits (S11=1 or -1). In both cases, S21 must be 0. This result is
consistent with the general formula of S-parameter modeling when S11 can
have arbitrary values (including the cases of S11=1 or -1). The treatment
for these specific cases of open and short circuits can be provided in the
Specification as examples instead of requirements of the Specification.
On the issue of setting S12=0, there have been IBIS discussions or
presentations recommending this. However, it is not necessary to impose this
condition on the analog circuits and it should not be treated as a
requirement of the BIS Specification.
Regards,
James Zhou
QLogic Corp.
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Bob Ross
Sent: Tuesday, March 20, 2012 2:57 PM
To: 'IBIS-ATM'
Subject: [ibis-macro] Analog Model Isolation Definition
All:
Per the discussion today on the block interface definition, here is a
derivation based on BIRD122 for just s2p 2-ports (but should apply to s4p
files with more math). It shows the gain sensitivity to the explicit S11
term for TX and S22 term for RX from a reference impedance definition (e.g.,
TX: S11=0 or 50 ohm to infinite impedance S11 = 1 and RX: S22=0 to zero
impedance S11=-1).
In both cases, the transfer function S21 term is changed by a factor of 2
(assuming no S12 term). This is equivalent to specifying the isolation
interfaces with a unity gain ideal voltage amplifier.
//www.freelists.org/post/ibis-macro/Eelement-in-analog-model-BIRD,1
Sorry, but some of the prior material may have involved some lost or private
e-mails and also a presentation or e-mail shown to the ATM committee
according to questions and exchanges in the Dec. 14, 2010 minutes including:
Walter showed an email from Fangyi:
- Fangyi: The equation is at the bottom
- Bob: We have defined S12 as zero
- The real voltage gain is a function of S11
- Todd: Is this because S11 can affect V1 and therefore V2?
- Fangyi: No
- If V1 was fixed V2 would still be affected by S11
- Bob: The defaults should be zero for series impedances and
infinity for impedances to ground.
http://www.vhdl.org/ibis/macromodel_wip/minutes/20101214/mikelabontecisco/Mi
nutes%20for%20the%2012-14-2010%20ibis-atm%20meeting/20101214.txt
The main point is that the complete interface needs to be known and defined
in the Specification (for S-parameters and perhaps different for a SPICE
model) to get the proper gain (S21 term).
Bob
--
Bob Ross
Teraspeed Consulting Group, LCC
http://www.teraspeed.com
bob@xxxxxxxxxxxxxx
Direct : 503-246-8048
Teraspeed Labs: 503-430-1065
Headquarters: 401-284-1827
Teraspeed is a registered service mark of Teraspeed Consulting Group LLC
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