[ibis-macro] Re: Analog Buffer Modeling - A Summary

  • From: "Walter Katz" <wkatz@xxxxxxxxxx>
  • To: "'IBIS-ATM'" <ibis-macro@xxxxxxxxxxxxx>
  • Date: Fri, 20 Jan 2012 08:05:59 -0500 (EST)



I have not received any comments that disagree with the following
statements, other than objections to having the ability to have four
canned models in addition to allowing general purpose ISS Buffer subckts.
I have no objection in principle to adding the canned Tstonefile proposal
in BIRD 144 (we can debate some of the details). Why object to the 4
canned ISS subckts that I have proposed. In summary:


1.       They satisfy the needs of all SerDes standards that have been
approved, and all SerDes standards in development.

2.       They accurately represent the LTI behavior of legacy IBIS models
(IV and VT tables).

3.       They represent circuits that EDA tools can easily and efficiently

4.       They make it easy for SerDes IC Vendors to accurately describe
the analog behavior of their models.

5.       There is nothing that prevents SerDes IC Vendors from creating
custom ISS Buffer AMI subckts.

6.       There is nothing that prevents IC Vendors from creating custom
ISS Buffer subckts for traditional single ended and differential buffers.


These are compelling arguments that IC Vendors and Users of IBIS AMI
models will support.


The argument that there will be a desire to add a plethora of new canned
models is specious.


No one has given an argument of what bad things can happen with the
inclusion of these canned models in the standard.


I hold these truths to be self-evident, please be prepared to voice your
objections at next week's IBIS-ATM meeting and the DesignCon IBIS Summit.




From: ibis-macro-bounce@xxxxxxxxxxxxx
[mailto:ibis-macro-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Wednesday, January 18, 2012 12:36 PM
Subject: [ibis-macro] Analog Buffer Modeling - A Summary




I will attend next Tuesday's meeting and will be prepared to discuss the
following. I will also be prepared to make a presentation to the IBIS
Summit on any of the following that you do not agree with:


1.       LTI vs Non-LTI Modeling

a.       I will propose that we table any IBIS-ATM discussion until
someone can present to IBIS a Channel that:


1.       A real IC Vendor SerDes Tx and Rx buffer

2.       A real Tx and Rx Package

3.       A real interconnect

When analyzing the Channel using

1.       Non-LTI Vendor Models

2.       An LTI approximation of the Models

                                                            iii.      Give
results that are different enough to cause the design engineer to make
substantively different design decisions.

2.       Can anyone provide an IBIS SerDes Tx and Rx Buffer that has a
constant impedance over the operating range of the Buffer that cannot be
accurately represented by either the proposed AMI_Thevenin_Tx and
AMI_Thevenin_Rx model? Please note the following subtle limitation of BIRD
116 described in 3.

3.       [External Model]/Language ISS assumes that the Analog Model LTI.
Therefore any Non-LTI affects that are caused by time variation that is
captured in the IBIS Rising and Falling Waveforms. The only way to handle
this is to change the D_to_A to contain a PWL.

4.       Can anyone provide an ISS subckt that represents a Tx or Rx ISS
SerDes buffer model that cannot be converted to an accurate Touchstone

5.       Can anyone point to an industry standard SerDes specification
(e.g. PCIeG3, PCIeG4, IEEE 802.3 bj, ap, kr) that does not specify
constrains on the analog behavior that cannot be represented by the
proposed AMI_Thevenin_Tx and AMI_Thevenin_Rx model?

6.       Does anyone disagree that any Tx or Rx analog LTI model can be
represented by one of the proposed models ( AMI_Tstonefile_Tx,
AMI_Tstonefile_Rx, AMI_Thevenin_Tx, or AMI_Thevenin_Rx model?





Walter Katz


Phone 303.449-2308

Mobile 720.333-1107


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