Hello Arpad,
Ground Bounce does not matter. Even if it did, you can't measure it. If you
can't measure it, then it is usually impossible (sometimes only extremely
difficult) to compute with full-wave solvers but in this case impossible. You
can approximate it at low frequencies if you use all partial-element (i.e.
partial inductance) models, which associate R/L parasitics with the GND nets.
As Scott points out, be careful not to mix-n-match global ground referenced
models with partial-element lumped models for your system analysis or your
results will not only represent incomplete ground bounce but will also be
wrong. However, S-parameters lose that information and cannot simulate absolute
level of ground bounce. If you believe you can measure ground bounce the please
describe the probe you will build for your oscilloscope or VNA.
With S-parameters you can use one VSS bump as a reference to which you
reference S-parameter ports defined at other VSS bumps. You can get the
distribution of VSS potential AT THOSE PORT BUMPD W.R.T. THE REFERNCE BUMP but
you will *never* know the potential of the reference bump. It could be 0.1V or
it could be 1000V. It simply doesn't matter to the chip, the package or the
system. Just like old tube TVs had high voltages and it didn't matter. At least
not until you make yourself a global ground path and touch the high voltage
coil. This is why improper use of global ground is not just an SI/PI issue but
a safety issue :)
Even the spatial distribution of VSS bump potentials (w.r.t. your reference VSS
bump) is not really important. What matters is the local potential of VDD
w.r.t. your local VSS and local signal w.r.t. local VSS. Ground bounce is a red
herring.
Cheers,
-Brad
From: ibis-interconn-bounce@xxxxxxxxxxxxx
[mailto:ibis-interconn-bounce@xxxxxxxxxxxxx] On Behalf Of Muranyi, Arpad
Sent: Monday, March 14, 2016 9:14 AM
To: IBIS-ATM; ibis-interconn@xxxxxxxxxxxxx; ibis-editorial@xxxxxxxxxxxxx
Subject: [ibis-interconn] Re: According to Scott McMorrow the Node 0 ground
assumption can be valid!
Walter,
Scott is absolutely correct. The catch is this statement:
"But, ground bounce inductance and resistance is then lumped into power
circuit and signal path circuits, and the discrimination between the these is
lost."
With that, the question becomes, how do we want to visualize
the results, and I feel that the answer is related to the
relativity theory. Do we want to see the dog wiggle its tail,
or the tail wiggle the dog... :)
More seriously, if we only care about how the receiver sees
the signal, we really don't need to know whether the receiver's
"GND" (i.e. reference) was rock steady or bouncing like crazy.
But if we want to make sure that the receiver's "GND" is not
bouncing like crazy, we will most likely want to see what it
does. But then the question becomes: "with respect to what?"...
Perhaps a better "GND" under the chip (GND plane of the PCB),
or the VRM half a mile away, or the ground stake at the utility
service entrance two miles away... :) I am trying to be funny
with some of this, but a package designer maybe serious about
wanting to know how good the GND traces are in his/her package...
Thanks,
Arpad
================================================================
From:
ibis-editorial-bounce@xxxxxxxxxxxxx<mailto:ibis-editorial-bounce@xxxxxxxxxxxxx>
[mailto:ibis-editorial-bounce@xxxxxxxxxxxxx] On Behalf Of Walter Katz
Sent: Sunday, March 13, 2016 7:06 PM
To: IBIS-ATM <ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>>;
ibis-interconn@xxxxxxxxxxxxx<mailto:ibis-interconn@xxxxxxxxxxxxx>;
ibis-editorial@xxxxxxxxxxxxx<mailto:ibis-editorial@xxxxxxxxxxxxx>
Subject: [ibis-editorial] According to Scott McMorrow the Node 0 ground
assumption can be valid!
All, (and Radek, Brad and Vladimir in particular)
Scott McMorrow writes:
Circuit theory says that we can go from a partial element system where ground
and power loops are fully modeled to a ground referenced system where node 0
ground is applied to every element in the path. But, ground bounce inductance
and resistance is then lumped into power circuit and signal path circuits, and
the discrimination between the these is lost. From a differential node voltage
perspective at the receiver, the result is the same. The voltage between the
signal and ground will remain the same. If there is a difference, then
somewhere in the circuit, the ground partial inductance has not been reduced
into the loop inductance for the signal path and power paths.
It is a pretty standard transformation from partial inductance/resistance
matrices to loop inductance/resistance matrices, and is covered quite
extensively in Brian Young's book, which is still the best on the subject. He's
been at Motorola and TI. I believe he's at TI now running their ASIC packaging
group.
http://www.amazon.com/Digital-Signal-Integrity-Simulation-Interconnects/dp/0130289043<https://urldefense.proofpoint.com/v2/url?u=http-3A__www.amazon.com_Digital-2DSignal-2DIntegrity-2DSimulation-2DInterconnects_dp_0130289043&d=CwMFAg&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-_haXqY&r=4FKJAciGx2YO_M9midmACQSNmiVxO3-RtONyf9pCZ_s&m=bQhV4a70HXXGMyA4AXTe1hCJ3AomEQFN3Q1b5DcjF90&s=GXhb182IZInPH4WolCF6SuyCMn5qD8zPgvEZI4PALNo&e=>
Walter
Walter Katz
wkatz@xxxxxxxxxx<mailto:wkatz@xxxxxxxxxx>
Phone 303.449-2308
Mobile 303.335-6156
