[ibis-macro] Re: A_to_D and D_to_A

  • From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
  • To: "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
  • Date: Thu, 12 Apr 2012 19:44:30 +0000


If you look at figure 7 on pg. 111 this may become clear.  In
that figure, "D_drive" is the "d_port", "my_drive" is "port1"
and "my_ref" is "port2".

I agree that the sentence:

"These entries are used for the
| user-defined port names, together with another port name, used
| as a reference."

is a little confusing, but in this sentence "user-defined port
name" seems to refer to "my_drive" for "port1" and the
"another port name" seems to refer to "my_ref" for "port2".

This is all for the model maker.  It is up to the model maker to
write this line in the .ibs file and invent their user defined
port names.  The EDA will only read this to create the netlist
for the simulation.

The polarity idea was mentioned here simply to describe a
possibility to flip "my_drive" and "my_ref" if the model needs
an inverted stimulus, since there is no such thing as
"D_drive_inverted" in IBIS.

The model maker should know which terminal is their "input"
and "reference" so they should know based on that how the
D_to_A converter's output should be connected to their model.
The spec clearly states which is which on the D_to_A converter:

"| Normally port1 accepts an input signal and port2 is the
| reference for port1."

I hope this answers your questions.



From: James Zhou [mailto:james.zhou@xxxxxxxxxx]
Sent: Thursday, April 12, 2012 2:08 PM
To: Muranyi, Arpad; ibis-macro@xxxxxxxxxxxxx
Subject: RE: [ibis-macro] Re: A_to_D and D_to_A

Hi Arpad,

When converting a logic '1' or '0' into an analog signal, Specification 5.0 has 
the following descriptions for D_to_A (page 109):
d_port port1 port2 vlow vhigh trise tfall corner_name

(paragraph-1)The d_port entry holds the name of the digital port. This

| entry is used for the reserved port names D_drive, D_enable,

| and D_switch. The port1 and port2 entries hold the SPICE,

| Verilog-A(MS) or VHDL-A(MS) analog input port names across

| which voltages are specified. These entries are used for the

| user-defined port names, together with another port name, used

| as a reference.

(paragraph-2)Normally port1 accepts an input signal and port2 is the

| reference for port1. However, for an opposite polarity

| stimulus, port1 could be connected to a reference port and
| port2 could serve as the input.

These two paragraphs need some serious clarification. For example,
(a) is the user or EDA tool expected to determine/assign whether a stimulus is 
of opposite polarity?
(b) What is the exact meaning of opposite polarity as used in here?
(c) Because the definition of d_port has already listed port1 port2 in such 
order, how could the model user and EDA tool determine which is input and which 
is reference (unless the Specification specifies that port1 should be signal, 
port2 should be reference)?
(d) in paragraph-1, what is  "another port name"? is it one of port1, port2 or 
"another" port3? There is obviously no port3 here.

James Zhou
QLogic Corp.

From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx> 
 On Behalf Of Muranyi, Arpad
Sent: Thursday, April 12, 2012 10:00 AM
To: ibis-macro@xxxxxxxxxxxxx<mailto:ibis-macro@xxxxxxxxxxxxx>
Subject: [ibis-macro] Re: A_to_D and D_to_A


[External Model] or [External Circuit] basically instantiates
a VHDL-AMS, Verilog-AMS, Verilog-A, or SPICE model.  The last
two can only have analog terminals (ports) on their interface.
The first tow may have analog or digital terminals (ports),
and it is up to the model maker to decide who they connect
their model to the outside world.

In IBIS, we assume that the EDA tool's stimulus is purely
digital (whether this is true in reality or not).  So the
stimulus for a driver, D_drive and the enable signal, D_enable
are considered a logic '1' or '0', not a voltage.

In order to drive the terminals of a purely analog model, you
need to have a D_to_A converter.  The drawing you are asking
about tries to illustrate how these converters are inserted
(automatically) by the EDA tool between its stimulus and the
analog terminals of the model.

Does this answer your question?


From: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx> 
 On Behalf Of Gregory R Edlund
Sent: Thursday, April 12, 2012 11:49 AM
To: ibis-macro-bounce@xxxxxxxxxxxxx<mailto:ibis-macro-bounce@xxxxxxxxxxxxx>; 
Subject: [ibis-macro] A_to_D and D_to_A

In reading through the BIRDs that have been tabled, I found myself going back 
to the original [External_Model] syntax from IBIS 4.2.  I'm having a hard time 
wrapping my head around the whole "analog-to-digital" thing.  Can anybody give 
me a simple example of when you might need a model like the one described in 
the 4.2?

|             +==================================================+
|             |                    "Model Unit"        +--------+|
|             |  +--------+                            |        ||
| D_receive --|-<| A_to_D |--<(analog receive ports)--<|        ||-- A_puref
|             |  +--------+                            | A pure ||
|             |                                        | analog ||-- A_pdref
|             |  +--------+                            |  I/O   ||
|   D_drive --|->| D_to_A |-->(analog drive ports)  -->| buffer ||-- A_signal
|             |  +--------+                            | model  ||
|             |                                        |        ||-- A_pcref
|             |  +--------+                            |        ||
|  D_enable --|->| D_to_A |-->(analog enable ports) -->|        ||-- A_gcref
|             |  +--------+                            |        ||
|             |                                        +--------+|
|             +==================================================+
|      Model Unit consists of SPICE, VHDL-A(MS), Verilog-A(MS) code plus
|                        A_to_D and D_TO_A converters
|            (references for D_to_A and A_to_D converters not shown)
| Figure 6: An analog-only Model Unit, using an I/O buffer as an example

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901

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