Draft 16 Technical Comment:
Page 29, bottom, the rule on the last line at the bottom under
Aggressor_Only needs to be changed from:
If a particular terminal is identified as Aggressor_Only, then the entire
path of the associated pin_name is to be considered Aggressor_Only.
To:
If a particular terminal is identified as Aggressor_Only at one Interconnect
Model interface, then the corresponding terminal at the other interface also
shall be identified as Aggressor_Only to describe the entire.
Reason:
Page 7 gives these rule under I/O pin_name rules:
o No I/O pin_name in a component may appear as a Pin_I/O terminal without
the Aggressor_Only column in more than one Interconnect Model in the
Interconnect Model Group.
o No I/O pin_name in a component may appear as a Buffer_I/O terminal
without the Aggressor_Only column in more than one Interconnect Model in the
Interconnect Model Group.
Without the suggested change, we can have Interconnect Models with
Aggressor_Only for just Pad_IO terminals and violate the intention of the
above statements (when we have pin to die pad and die pad to buffer
Interconnect Models referenced in the same Interconnect Model Group).
Furthermore, we can have one pin-to-buffer Interconnect Model with a Pin_I/O
terminal as Aggressor_Only, and a different pin-to-buffer Interconnect Model
with the same Buffer_I/O terminal as Aggressor_Only - both referenced from
the same Interconnect Model Group.
Also, the page 7 bullets need to be expanded when we have a die pad
interface because these Interconnect Model references would be allowed in
one Interconnect Model Group:
[Interconnect Model] A
1 Buffer_I/O pin_name 1 Aggressor_Only
2 Pad_I/O pin_name 1 Aggressor_Only
3 ...
[Interconnect Model] B
1 Pin_I/O pin_name 1
2 Pad_I/O pin_name 1
3 ...
[Interconnect Model] C
1 Buffer_I/O pin_name 1
2 Pad_I/O pin_name 1
3 ...
[Interconnect Model] D
1 Pin_I/O pin_name 1 Aggressor_Only
2 Pad_I/O pin_name 1 Aggressor_Only
3 ...
The above case is legal because there is only one Aggressor_Only for
Buffer_I/O pin_name 1, and only one for Pin_I/O pin_name 1. A can connect
to B, and C to D, but that produces two complete pin_name 1 Aggressor_Only
paths. The rules need to be expanded to exclude this situation through
references within an Interconnect Model Group.
Bob
