[hsdd] High-Speed Digital Design Newsletter - - Jitter Tracking
- From: "Howard Johnson" <howie03@xxxxxxxxxx>
- To: <hsdd@xxxxxxxxxxxxx>
- Date: Wed, 8 Sep 2010 09:52:55 -0700
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Public Seminar Schedule, taught by Dr. Howard Johnson
<http://www.sigcon.com/seminars/seminarHSDD.htm> High-Speed Digital Design
Silicon Valley, CA
Huntsville, AL
Coming Spring 2011
<file:///C:/Sigcon%20web%20site/Pubs/seminars/HuntsvilleALHSDD.htm> October
25-26, 2010
<http://www.sigcon.com/seminars/seminarAHSSP.htm> Adv. High-Speed Signal
Propagation
Huntsville, AL
<file:///C:/Sigcon%20web%20site/Pubs/seminars/HuntsvilleALAHSSP.htm>
October 27-28, 2010
<http://www.sigcon.com/seminars/seminarHSNG.htm> High-Speed Noise and
Grounding
Silicon Valley, CA
Coming Spring 2011
Jitter Tracking
HIGH-SPEED DIGITAL DESIGN - online newsletter -
Vol. 13 Issue 02
Seattle, Pittsburgh and Huntsville
My Fall 2010 seminar season kicks off with private classes in Seattle and in
Pittsburgh. While in Pittsburgh I get to visit my daughter, who just
enrolled as a freshman at the Carnegie-Mellon School of Computer Science.
After that I fly to Huntsville, Alabama to teach my final public seminars of
this year: High-Speed Digital Design (Oct. 25-26) and Advanced High-Speed
Signal Propagation (Oct. 27-28). I will also be speaking at the Huntsville
chapter of the IEEE EMC Society on the evening of October 28. I look forward
to seeing my colleagues in the Southeast.
About this article:
The proliferation of serial standards makes jitter, and knowledge of how to
deal with it, an important part of our daily lives. Today's installment is
one of a nine-part series on that issue. Jitter will become a major theme
for this newsletter throughout the remainder of the year into 2011.
I'd like to record these and other talks in a multi-media format. If you
have access to equipment, facilities or other support that could help make
that happen, please drop me a line: howie03@xxxxxxxxxx .
Jitter Tracking
By Dr. Howard Johnson,
Imagine a serial-data clock recovery system based on a phase-locked loop
(PLL) circuit. Presented with a sudden change in input timing the PLL
responds sluggishly, taking many cycles to track the new incoming phase.
That is part of its function. A sluggish response prevents small deviations
in received timing from jolting the recovered clock out of kilter.
The response time of the PLL partitions the world of all possible input
timing variations into two categories: those variations so slow that the
PLL easily tracks them, and other, faster variations that the PLL cannot
track. The slow variations we call wander, the fast ones jitter. Note that
this definition of wander and jitter depends entirely upon the
characteristics of the PLL at hand. Another circuit might perceive wander
and jitter differently.
Being a time-oriented thinker, I describe the dividing line between wander
and jitter as something that depends on the rise or fall time of the
incoming variations. If you like the frequency domain, then you may imagine
that the dividing line depends on the frequency of the incoming variations.
Either way works-these are interchangeable ideas.
A deep grasp of jitter, wander, and how a PLL reacts to them will help
refine your understanding of serial data communications. It will also help
you debug jittery reference clock problems and design systems that work
reliably in the face of noise.
If you already know about phase tracks then you may step out for a cup of
tea while I run through the next part of this discussion. Of course, I can't
promise that I won't say something important..
Phase track
We are all used to seeing plots of voltage versus time. The concept of
jitter analysis requires that you master a new skill: you must imagine a new
track of information running parallel to the voltage track. The new track
encodes nothing but pure timing information.
The new track is a series of impulses. At the location of every
zero-crossing position in the original voltage track, the new timing track
records an impulse whose height indicates whether that edge appears early or
late compared to a theoretically ideal signal.
Figure 1 shows the new timing track running alongside the original voltage
plot. The timing track extends sideways into a third dimension representing
the "early or lateness" of each edge. This new vector of timing information
is called a "phase track".
Figure 1-A phase track represents the complete range of all timing
variations in the signal.
Moving from left to right in the figure, the first nine edges all arrive
early. The next three are late. The degree of earliness or lateness is
difficult to discern in the voltage plots, which is precisely why it helps
to show the phase track. If you look very carefully at the points where the
purple voltage track touches or leaves the bottom axis you will see that the
first nine transitions precede their respective phase track impulses. The
next three fall slightly behind. The phase track impulses are drawn on a
grid of ideal timing locations.
Whenever you encounter a synchronous digital signal, think about the phase
track.
If you work with RF circuits, you may be more comfortable thinking of the
phase track as the output of an ideal phase detector, or perhaps the
demodulated Q-channel output of a phase modulated receiver. These are
similar concepts.
A PLL is a filter
A phase-locked loop (PLL) circuit responds not to a voltage waveform, but a
phase track. A PLL transforms the incoming phase track into a new signal
with a different phase track.
A PLL phase-track transformation has two important properties: it is linear,
and it is time-invariant. The linear property implies that, within its
tracking limits, the PLL responds linearly to timing variations in the
incoming phase track. The time invariant property means that it responds the
same way at all moments; the circuit has no internal memory that modifies
its behavior versus calendar time.
Any circuit that responds in a linear and time-invariant fashion to its
inputs constitutes a type of linear filter. Those of you steeped in DSP
theory may recognize the PLL is a discrete-time filter, meaning that it
accepts inputs and modifies it outputs only at discrete times (signal
edges).
A PLL circuit forms a specific type of filter called a low-pass filter. That
happens because, by design, a PLL tracks slow changes in timing that occur
over spans of time longer than its characteristic response time. The same
PLL cruises through short, quick changes without reacting. Any filter that
passes slow changes while filtering out quick ones must be a type of
low-pass filter.
Mechanical Low-Pass Filter
If you are going to work with PLL circuits it is important that you fix in
your mind a concrete image of how a low-pass filter interacts with a signal.
Towards that end, I shall build a simple mechanical tracking device that
emulates the low-pass filtering action of a PLL.
The body of my tracking device is made of wood. It holds a felt-tip pen so
positioned that the tip drags on a sheet of paper. When you pull the string,
the pen follows, leaving a mark. Figure 2 illustrates the device in action.
In plan view, the wooden body appears triangular (Figure 3).
Figure 2-(Side view) A string drags the tracking device across a sheet of
paper.
On a clean sheet of paper I draw a waveform to serve as input to the system.
Call it the "source track". The source track could represent any signal,
including possibly the phase track of an incoming serial-data channel.
To operate the tracking device, I place my marker on the source track. The
marker is just a piece of cardboard with crosshairs that helps me center the
string precisely on the waveform. The string connects the source marker to
the tracking device, dragging it along.
Figure 3-By hand, carefully advance the source marker along the
source waveform, dragging the pen behind.
As I advance the marker, the pen creates a new waveform (dotted red line in
Figure 4). The new waveform is a filtered version of the source track. The
filter appears much like a first-order, linear, time-invariant low-pass
filter-similar to the response of a simple PLL circuit. The longer you make
the string, the more sluggish the response. If you can mentally imagine the
pen dragging behind the marker, you've got yourself a good mental model of
PLL behavior.
Figure 4-The pen traces a low-pass filtered version of the source waveform.
NOTES ABOUT CONSTRUCTION: (1) The wooden triangle does not need wheels, it
just drags. (2) Use a felt-tipped pen. (3) You do not need an elaborate
source marker. A pencil with a string tied near its tip will do. (4) The pen
trails the source by the length of the string. I draw the source waveform on
white paper first and then cover it with an overlay of transparent film. Let
the pen draw on the film. When you are done, slide the film horizontally to
align the output timing with the input drawn on the white paper. (5) Keep
the vertical displacement small compared to the length of the string and use
a long strip of paper. (6) Don't go too fast.
The animation <http://www.sigcon.com/Video/00377-filter.wmv>
Video/00377-filter.wmv illustrates the operation of my tracking system. The
animation depicts step response, jitter filtering, and wander-tracking
behavior.
NOTE: If you would like to see a tracking a machine in action, I made a
quick version out of a clothes pin and a felt-tip pen for Bob Pease's Analog
by Design show over at National a few months back. It worked beautifully.
Here's the link. You may need to register to see the show:
http://www.national.com/profile/os.cgi?EventID=022707
Now, whenever I think about serial data, I imagine the phase track laid out
sideways, as in Figure 1, the little tracking device from Figure 3 scurrying
along beside, and Bob Pease, smiling.
Best Regards,
Dr. Howard Johnson
_____
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code NL10.
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