[haiku-development] Re: ARM port status and info
- From: johannes <johanneswi@xxxxxxxxx>
- To: haiku-development <haiku-development@xxxxxxxxxxxxx>
- Date: Fri, 05 Feb 2010 16:02:52 +0000
Excerpts from Michael Zucchi's message of Fri Feb 05 07:49:47 +0000 2010:
> Hi Matt & Johannes,
>
>
> It does this following before it crashes inside vfprintf(), (if my bodgy
> exception handler is accurate anyway). (i added a bit more debug too)
>
> [ mostly mmu code output ]
>
> platform_init_video()
> video framebuffer: 0x88000000
> video mode: 1024x768x16
> platform_switch_to_logo()
> arch_set_default_video_mode()
> arch_set_video_mode 1024,768 @ 16
> set video mode: 0x00000000
>
> [ lots of mmu code output ]
>
> NEXT VIRRUADRSSS: 80232000
> ADDR: 80232000
> map_page: vaddr 0x80232000, paddr 0x81251000
> map_page: pageTable 0x81112800
> map_page: inserting pageTable 0x81112800, tableEntry 50,
> physicalAddress 0x81251000
> map_page: done
> video_display_splash: 0x00000000
> Welcome to the Haiku boot loader!
> platform_add_boot_device
> platform_add_block_devices
> user_menu: enter
> Exception: Data Abort
> pc: 8000dcd4 sr: 200001d3
> r0: 0000000e
> r1: 00000000
> r2: 0000000e
> ...
>
How do you boot the whole thing? The problem is that it does not find the
memory disk that it should get from u-boot (look at platform_add_boot_device in
src/system/boot/platform/u-boot/devices.cpp and start2.c) If you use the
created haiku_loader.ub it should put the memory disk image at the right
position..
> > so empty stubs are enough right now) In the blog he also writes that
> > he fixed the code to use the new mmu-table format (but I don't know
> > if this is absolutely needed since my reading of the documentation
> > leads me to believe that the Cortex A8 does still support the old
> > format)
>
> Well, the ARM ARM, B4.9.2, says this about CP15, C1:
>
> XP (bit[23]) Extended page table configuration. This bit configures
> the hardware page table translation mechanism:
> 0 = VMSAv4/v5 and VMSAv6, subpages enabled
> 1 = VMSAv6, subpages disabled.
>
> Then in the Cortex-A8 TRM, section 3.2.25, for the c1 control
> register. Bits 14-24 are marked as 'reserved', and in the bit
> definitions it is listed as as 'This field returns 11'b01100010100
> when read'. i.e. bit 23 always on, subpages disabled, etc.
>
hm then I must obviously have misread something ;)
> Regards,
> Michael
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